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UCIe or Universal Chiplet Interconnect Express is the fastest growing chiplet interconnect standard that enables a future where a catalog of chiplets will be available to mix and match based on the chip designs in the sphere of AI, network computing, etc. It is a multi-layer, multi-protocol with well-defined die-to-die interfaces.
Its stack is broken down into three major layers, namely:
Each of the above-mentioned layers has a wide array of capabilities, such as multi-protocol support (CXL, PCIe, and Streaming), varying interface widths and data rates, protocol multiplexing, and packaging options, to name a few. This gives options to design simple as well as the most sophisticated chiplets based on the end application. As an example, one version of Physical Layer Chiplet design could have Standard Packaging support and another version could support Advanced Packaging with increased link width.
Let us look at the various topologies which leverage different UCIe interfaces:
Exciting for sure, but strenuous for the design verification teams who are back on their drawing board drafting strategies to cater to such humongous prospects! Testbenches should leverage verification components that cater to the unit level, subsystem level, and system level during various development stages. The need of the hour is having a scalable architecture with minimum configuration level changes.
The Cadence UCIe VIP team foresees the situation, and as UCIe 1.0 is just the start of the Chiplet Interconnect journey, the verification challenges are only going to become more complex in the next few years.
Hence, the VIP has a state-of-the-art architecture with a range of flexible configurations and capabilities to support all these topologies. Each layer can serve as an independent component for unit level verification. All layers combined serve goals for subsystems and systems testbenches.
More to come, stay tuned …
Semiconductor companies can start using it to fully verify their design and achieve functional verification closure on it within no time. More details are available on the Cadence Verification IP Portfolio.
For more information on UCIe in general, see the UCI Express website