University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level Synthesis

Today we issued a Japan-only press release announcing a high-level synthesis joint development program with the University of Aizu. This is Japan's first university-level course teaching high-level synthesis for semiconductor design. Here is the link to the full release, and if you can't read it then Google Translate should help:

http://www.cadence.co.jp/news/h24-12-17.html

This is an important milestone, because while Japan has been the leader in adoption of high-level synthesis for production hardware design, there has been no formalized training program. If you remember the panel discussion at this year's DAC, it was widely agreed upon that the biggest impediment to broader adoption of high-level synthesis is developing the skill set required to be successful.

In short, there have been many hurdles to widespread usage of HLS for chip design, but given the latest generation of tools and methodologies, the last remaining hurdle is the unique skill set required to be successful. Specifically, the input language for HLS if you're using it for production chip design and verification is SystemC, which is a hardware-specific class library for C++. Like RTL synthesis, generating hardware that meets your Quality of Results goals requires hardware micro-architecture expertise. However, most engineers with that expertise are rusty when it comes to C++.

For today's hardware designers and architects, learning C++ and SystemC is not easy. We have had customers do it, but to sufficiently ramp up in C++ requires a few months of effort, which is difficult given today's lean staffing levels and demanding schedules. There are a lot of great resources out there for learning the language and methodology. But for today's hardware designers the one resource that is often lacking is free time. Hopefully forward-looking companies will make that investment in order to attain the benefits that higher-abstraction design and verification delivers.

For the longer term, we are trying to help universities prepare their graduates for the way design and verification will be done (taking Wayne Gretzky's advice to go where the puck is going to be). Japan is not the first country to have a university program for this area. Both Dr. Luca Carloni at Columbia University and Dr. Luciano Lavagno at Politecnico di Torino in Italy have incorporated it into their courses. And we are working with some other universities to ramp up courses that utilize the TLM-Driven Design and Verification Methodology book in conjunction with our C-to-Silicon Compiler HLS software. It is thanks to Professor Saito's great efforts in the translation of the TLM Design and Verification Methodology book into Japanese that this is now more accessible to the Japanese community.

So if you are an engineering manager looking to hire engineers to lead your methodology transition to the next level of abstraction, then these programs are the best place to start. And if you are from a university looking to incorporate this material into your curriculum, then we look forward to working with you!

-Jack Erickson