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In PCI Express (PCIe) devices, there is a need for testing near-worst-case inter-symbol interference (ISI) and cross-talk so as to ensure data flow with minimal distortion and noise. To accommodate this in PCIe, we have a separate LTSSM state as polling.compliance state. This phase will generate patterns named compliance pattern, modified compliance pattern, jitter pattern, and toggle pattern (a new feature added in PCIe 6.0 Spec). Based on the speed and the settings, the patterns are transmitted in the Polling.Compliance state.
The ways to enter Polling.Compliance state are:
Figure 1: Polling States
Upon entry to Polling.compliance, the compliance pattern settings having different transmitter preset and de-emphasis values are transmitted based on the operating speed. Based on the target speed the device enters Polling.Compliance and changes the rate to the given rate and then transmits the compliance patterns.
Figure 2: Preset Encodings in different rates and settings
In Flit mode Compliance TS1 are sent by THE transmitter, and the compliance TS1 contains the number of the settings the transmitter will apply. With respect to PCIe 6.0, there are further additions to the compliance pattern. Since Gen6 follows PAM4 encoding, the compliance pattern has been modified as per 1b/1b encoding.
In 1b/1b encoding the TS1/TS2 Ordered Sets have also been changed where the compliance bits position has been modified. Now, training controls are repeated in Symbol 6 and Symbol 14 in TS1/TS2 Ordered Sets with 1b/1b encoding.
Figure 3: TS1/TS2 in 1b/1b encoding
Additional settings for 64 GT/s rate have also been added.
Figure 4: Compliance Pattern Settings
Figure 5: Jitter pattern in 1b/1b encoding
Two types of toggle patterns named as High Swing Toggle Pattern and Low Swing Toggle Pattern:
As per PCIe 6.0 spec, the patterns are defined for different settings and different lanes. This gives coverage of all patterns of respective speed to be covered for all the lanes that detected receiver and provides robustness to the testing.
Data on SerDes interface had to be reconstructed on the reception side as the data had shifts and the device to lock on the data was received. Normally, on SerDes Aligner, the lock happens on seeing EIEOS but when in compliance state, some settings do not have EIEOS, which makes it difficult to lock. So, the device must be capable enough to lock on more than one pattern to overcome this issue.
In summary, with the increase in complexity of the new additions in PCIe 6.0 features, the verification challenges increase. Mostly, with early adopted features like PCIe 6.0, the task of providing the best VIP solution catering PCIe 6.0 features becomes more challenging. Cadence's PCIe 6.0 VIP is fully compliant with the latest PCIe 6.0 specification and provides better solutions to verify complex design aspects and features.