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Igor Krause
Igor Krause

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Verification IP
PCIe 6.0

Unraveling Precision Time Measurement (PTM)

1 May 2026 • 5 minute read

Introduction

Precision Time Measurement (PTM) is an optional capability for communicating precise timing information between components. PTM enables precise coordination of events across multiple components with independent local time clocks. Such precise coordination is difficult, given that individual time clocks have differing notions of the value and rate of change of time. PTM is used in links/domains where the system needs its devices to have precise coordination. Good examples of systems that may take advantage of PTM include media processing, telecommunications, and scientific instrumentation.

PTM Theory and Operation

PTM enables components to calculate the relationship between their local times and a shared PTM Master Time: an independent time domain associated with a PTM Root.

Each Upstream Port initiates PTM dialogs to establish the relationship between its local time and the PTM Master Time provided by the Root Port.

PTM-capable components can make their PTM context available for inspection by software, enabling software to translate timing information between local times and the PTM Master Time. In turn, this capability enables software to coordinate events across multiple components with very fine precision.

  • PTM Requester - A Function capable of using PTM as a consumer associated with an Endpoint or an Upstream Port.
  • PTM Responder - A Function capable of using PTM to supply the PTM Master Time associated with a Port or an RCRB.
  • Time Source - A local clock associated with a PTM Responder.
  • PTM Root - The source of PTM Master Time for a PTM Hierarchy. A PTM Root must also be a Time Source and is typically also a PTM Responder.

PTM Link Protocol

A PTM dialog is defined as a matched pair of messages consisting of a PTM Request and the corresponding PTM Response or PTM ResponseD message.

The timestamps captured during the PTM dialogs enable the calculation of the timing relationship between the PTM Requester and PTM Responder (please see the image below for reference). The value (t3-t2) measures the time consumed by the PTM Responder for a given PTM dialog. The time (t4-t1) is the time from request to response. Therefore, ((t4 - t1) - (t3 - t2)) effectively gives the round-trip message transit time between the two components, and that quantity divided by 2 approximates the Link delay - the time difference between t1 and t2.


PTM Link Protocol
  • A PTM Requester must update its stored t1 timestamp when transmitting a PTM Request Message, even if that transmission is a replay.
  • A PTM Responder must update its stored t2 timestamp when receiving a PTM Request Message, even if the received TLP is a duplicate.
  • A PTM Responder must update its stored t3 timestamp when transmitting a PTM Response or ResponseD Message, even if that transmission is a replay.
  • A PTM Requester must update its stored t4 timestamp when receiving a PTM Response Message, even if the received TLP is a duplicate.

The PTM Master Time field is a 64-bit value containing the value of PTM Master Time at the receipt of the PTM Request Message for the current PTM Dialog. In the shared image, for the 2nd PTM dialog, this is the PTM Master Time at time t2'.

The Propagation Delay field is a 32-bit value containing the interval between the receipt of the PTM Request Message and the transmission of the PTM Response Message for the previous PTM dialog. In the shared image, for the second PTM dialog, this is the time interval between t2 and t3 captured during the first PTM dialog.

In NFM, Timestamps must be based on the STP Symbol or Token that frames the TLP, as if observing the first bit of that Symbol or Token at the Port's pins. The image below shows the PTM Request and Response Messages for Non-Flit Mode:

 PTM Request/Response Message - Non-Flit Mode

PTM ResponseD Message - Non-Flit Mode

In Flit Mode, timestamps for PTM messages are measured at the Flit level rather than at the TLP level. There is the bit "PTM Message contained in this Flit" in the Flit_Marker field, which signals the presence of a non-nullified PTM Message inside the Flit. The PTM timestamps must be based on the Flit_Marker field.

The images below show the PTM Request and Response Messages for Flit Mode, and the Flit_Marker indicator:

 PTM Request/Response Message - Flit Mode
 PTM ResponseD Message - Flit Mode
 Flit_Marker

PTM Extended Capability Structure

The Extended Capability structure is required for any port of the Root-Complex that supports PTM and in only one function of the Endpoint. The images below show the PTM Capability and Control registers:

 PTM Capability Register
 PTM Control Register

Enhanced Precision Time Measurement (ePTM) places additional requirements on PTM Devices. It must be implemented in all PTM devices that support Flit-Mode. Support for ePTM is indicated by the ePTM Capable bit.

PTM Verification Challenges and Solutions

The PTM feature introduces the PTM Request and Response Messages, whose proper utilization requires careful coordination between the devices. The new Messages may be checked to avoid any violation of the reserved fields, time accuracy, and data precision.
The PTM Extended Capability structure brings a new set of configuration registers. Verifiers must guarantee that the device's capability register correctly indicates feature support, that the control register is configured with the proper value, and that the feature is not enabled before the system is ready. Users can take advantage of VIP's error messages to identify Spec's violations more efficiently.

Verifying the PTM dialog can be really challenging. The PCIe specification defines the exact gathering point for the timestamp values. But at the same time, the devices may hold a small to moderate delay for processing incoming data, which may compromise the timestamp gathering value. The PTM dialog verification requires precise timing analysis.

Please refer to the VIP PCIe User Guide for more information on VIP PTM implementation and configuration.

Learn More

  • For more information on how Cadence PCIe Verification IP and TripleCheck VIP enable users to confidently verify IDE, see our VIP for PCI Express, VIP for Compute Express Link, and TripleCheck for PCI Express
  • For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.
  • If you have more feedback or need more information, reach out to us at talk_to_vip_expert@cadence.com.

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