Update to the OVM Register Package

OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects.

The Cadence genIES team has been remiss since the demise of the OVM World, which left the OVM community to use OVM_RGM 2.5.  We did try to post to UVM World, but that is really dedicated to the UVM.  Therefore, we will be picking up the contribution thread and maintaining the Cadence contributions to the OVM here.  By far the most popular is the register package so we are posting the latest version 2.7.1 here.  We've included the release notes from 2.6, 2.7, and 2.7.1 to bring you all up to date.  Of course, the complete release note history is in the tarball. 

Release Notes for OVM_RGM2.7.1
Nov 18, 2011

** Bug Fixed:
   ¯¯¯¯¯¯¯¯¯ 
  ¤ Fixed issue with backdoor read for special read fields
  ¤ Fixed issue with sync for special read fields

Release Notes for OVM_RGM2.7
Sept 21, 2011

** Bug Fixed:
   ¯¯¯¯¯¯¯¯¯ 
  ¤ Walking one sequence did not create the regOp when writing
  ¤ Mode based register enum field macro having wrong case statement
  ¤ Typo in DPI file (vhpiHandleT changed to vpiHandle)
  ¤ Check for address overlap for indirect / shared and mode-based corrected

** Enhancements:
   ¯¯¯¯¯¯¯¯¯¯¯¯ 
  ¤ Added support for mode based registers having separate storage

Release Notes for OVM_RGM2.6.1
Aug 18, 2011

** Bug Fixed:
   ¯¯¯¯¯¯¯¯¯ 
  ¤ Fixed issue with syncing to VHDL
  ¤ Register overlap check error with end address
  ¤ Backdoor read of register fields was not properly masked
  ¤ Filtering of registers having unknown value is now only for rd_all regs seq

** Enhancements:
   ¯¯¯¯¯¯¯¯¯¯¯¯ 
  ¤ Allowed backdoor write to read-only fields
  ¤ Allowed register's reset value over-ride using plusArgs
  ¤ Added register array delete at the end of built-in-seq
  ¤ Added support field-level backdoor access for shared register
  ¤ Modified shared_reg_backdoor example and added ipxact file
  ¤ Removed all uvm deprication warnings from examples
  ¤ Added more support for VHDL backdoor std_ulogic_[ports|signals|vector_signals]
  ¤ Modified all headers of XML files to get schema from http
  ¤ Added objection to built-in-sequences
  ¤ Added a global field to mask-out comparison of all non-read-write fields
  ¤ Added a global field to enable warning when accessed address is outside container

 =Incisive genIES Team