USB4 Version 2.0 – Link Configurations

USB4 Version 2.0 specification was released by the USB Promoter Group earlier this year. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode.

The new version brings with it the possibility of configuring the USB4 link in asymmetric mode or transitioning to it from the symmetric mode.

There are a few changes in the terminologies as well for describing a USB4 link. The term Dual-Lane is no longer used. Instead, a USB4 link that uses two bonded lanes to transmit and receive data is called an Aggregated Link, which can be a Symmetric Link or an Asymmetric Link.

• A Symmetric Link is an Aggregated Link that operates with two transmitters and two receivers on each side of the link. This is what used to be called a Dual-Lane Link for Gen 2 or Gen 3 in USB4 Version 1.0 Specification.
• An Asymmetric Link is an Aggregated Link that operates with three transmitters and one receiver on one side of the link and three receivers and one transmitter on the other side of the link. It is supported only in Gen 4 Links.

The following diagram depicts various possible link configurations that this new version of the specification puts forth.

The specification defines mechanisms to transition from one link configuration to the other, and vice-versa. For example, a Gen 4 Symmetric Link can be transitioned to a Gen 4 Asymmetric Link, given all the various conditions for it are satisfied, and it can be brought back to being a Gen 4 Symmetric Link as well. It can all be achieved by appropriate programming of fields of port and lane adapter configuration spaces, high-speed link ordered sets, sideband channel transactions, and LFPS signaling.

A high-level depiction of one such transition is shown in the diagram below.

USB4 VIP supports different types of link configurations and capabilities to do link transitions as part of a comprehensive set of new features of the USB4 Version 2.0 specification. These features are enabled on the existing architecture of USB4 VIP. This allows current users to easily enable the USB4 Version 2.0 features in their existing USB4 verification environment.

Cadence has a mature Verification IP solution, for the verification of various aspects of USB4 Version 2.0 and Version 1.0 design, with verification capabilities provided to do a comprehensive verification of these.

You may refer to https://www.cadence.com/en_US/home/tools/system-design-and-verification/verification-ip/simulation-vip.html for more information.