VIP Following OVM Frees Users to Choose SystemVerilog and e

Back in November Cadence introduced a vastly expanded verification IP portfolio using the OVM.  By using the OVM, Cadence chose a methodology architected for multiple verification languages.  Beyond the fact that Cadence has the broadest IEEE standard support in the industry, why would any other company use a methodology and verification IP for use with multiple languages?

It turns out that each of the IEEE languages used for verification -- SystemVerilog and e -- offer unique value. Several verification leaders have noted this in their blogs, JL Gray being one of them.  Its likely that this trend will follow the digital design side where Verilog, VHDL, and SystemC already mix and AMS which, by definition, involves multiple languages.

Mark Litterick from Verilab observed that methodology can transcend language in his recent Embedded.com article entitled "Architecting the OCP uVC verification component."  In the article, Mark says "In the uVC, example the profile library and user extensions are all derived from a single base-class containing all of the OCP configuration parameters. This base-class can be in e, if a Specman layer is present, or in SystemVerilog otherwise."

This is only possible because eRM and OVM with SystemVerilog share the same methodology.  This unique capability allows Verilab customers to select the language that best suites their needs while enabling Verilab itself to support the largest possible customer base.

Choice.  Whether it is verification languages, technology suppliers, or VIP suppliers the OVM is the only methodology that provides real choice. Do you code primarily in e? SystemVerilog? What about your vendors?  What about your suppliers?  If you start with OVM, you have the lowest risk in the multi-language verification world.

=Adam Sherilog

PS:  If you are shopping for OCP, don't forget Cadence OCP.  Remember, vendor choice assures the best technology for the customer! :-)