Get email delivery of the Cadence blog featured here
The industry-standard ARM AMBA® 5 protocol specifications continue to evolve, further improving performance and efficiency of key ARM architecture features. Besides the updates of powerful AMBA CHI (Coherent Hub Interface) specification with Issue D and Issue E features (which will be discussed in-depth in upcoming blogs), ARM invested in updating their highly successful and very popular AMBA AXI, ACE and AHB on-chip protocols to feature-align them to AMBA CHI specification.
The AMBA ACE5, ACE5-Lite, and AXI5 protocols extend prior specification generations and add several important performance and scalability features which closely align these protocols to AMBA CHI.
Some of the new features include:
The Issue G update adds a very important Interface Parity Protection functional safety feature (which is a must in automotive applications) as well as Memory Partitioning and Monitoring (MPAM) feature which helps with the system monitoring and resource allocation.
Among the Issue H updates, undoubtedly, the most important feature is the Memory Tagging Extensions (MTE) which significantly improves security of ARM architecture and provides a mechanism to detect memory safety violations (which could be exploited in cyber-attacks).
The AMBA AHB protocol added a few features to align itself to the latest in AXI, ACE, and CHI protocols. Here are some of the new AHB specification properties:
All the latest AXI, ACE, and AHB features are fully supported in Cadence dual-mode ACE/AXI and AHB Verification IPs (VIPs). We will cover the key features of these VIPs in the upcoming blog and see how they interact with other key components of properly constructed verification environments. Stay tuned for the upcoming blogs!