What's The Best Way To Reduce SoC Development Costs?

Before I got started with my DAC 2010 customer meetings on Monday morning, I stopped by the DAC Pavilion to hear what Gary Smith had to say in his "Trends and What's Hot at DAC" session. I was very pleased to hear Gary say that Virtual Platforms are the most promising way to reduce design costs. Richard Goering did a good job summarizing the main points if you are interested in more details. Today, I will push a little deeper and identify what to look for in a Virtual Platform that will help cut SoC design costs. I will also share some trends I observed at DAC.

Here's the start of a list of things to look for:

• Modeling approach based on SystemC and TLM 2.0 standards
• High-speed simulation; performance is king in Virtual Platforms used for Embedded Software, and there is no such thing as too fast
• Integrated CPU models
• Automated non-CPU model creation with considerations for both Virtual Platform and High-Level Synthesis
• IP Model packaging and assembly for correct by construction platform creation
• Solid embedded software debugging tools; especially for operating system debug and multi-core systems
• Design-aware programmer's view of the system; including registers and memory
• System analysis for tuning HW/SW performance
• Debugging and analysis features that work without special model instrumentation
• Ability to easily export the Virtual Platform for users in other groups and companies
• Connections to other design and verification activities; not a point tool that only addresses Virtual Platform
• Verification, Verification, Verification; it's pretty obvious, but the best way to reduce costs is to decrease the time it takes to find and fix bugs

DAC Trends

One trend at DAC has been the Missing Model Syndrome related to IP purchased from other companies that does not come with suitable models for integration into a Virtual Platform. This should be a required deliverable, but is still missing or lagging in many cases.

Another trend I observed is that multiple companies described how they are planning to overcome the organizational barriers between hardware and software groups by having the hardware and verification teams take over the responsibility of low-level software APIs. In the past, many verification teams have written C test programs and hardware testbenches to verify the hardware. They even pass these tests to software engineers in the form of C fragments or e or SystemVerilog sequences to tell the software team how to program the device for configuration or to do certain operations. Delivering a combined hardware and software package to the software team is a good next step for many companies to consider.

The last trend that was common among users was the need for a good platform assembly tool to quickly create variations of Virtual Platforms. Today, many users find manual text editing to be time consuming and difficult to get right. The result is wasted time spent debugging every time the platform is modified.

Remember, Virtual Platforms are only a means to get to the end goals of higher quality software in a shorter time, which will ultimately lower SoC design cost.

At DAC this year it's clear that Virtual Platforms are no longer a side project that is separate from main design activities with insufficient resources assigned to it. Users are now serious about learning how to create models and platforms and understand that they can't just rely on an EDA vendor to show up and provide everything they need. Making Virtual Platforms a key step in the design process ensures that the promised cost savings will be realized.

I'm always interested to hear additional keys to success with Virtual Platforms or other trends related to embedded software development.

Jason Andrews