Why 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?

Cadence Multi-Platform Verification improves functional coverage and verification time

The recent advancements in the automotive industry, such as ADAS/AV, and infotainment all depend on reliable in-vehicle communication. To keep up with the high-speed, low-cost, and optimized EMC and weight constraints, the automotive industry is moving from legacy buses to automotive ethernet, with 10BASE-T1S, ethernet sub systems emerging as a key technology for shared, multidrop connectivity. These subsystems must support diverse multidrop configurations while interacting reliably with safety-critical domains such as ADAS and zonal controllers.

However, such advancements have led to increasing challenges for design teams, as they face issues verifying these 10BaseT based networking subsystems thoroughly enough to guarantee no surprises in silicon. In addition, as protocols expand and multidrop topologies emerge, traditional single‑platform verification (simulation) methods struggle to deliver sufficient coverage and timely signoff and guarantee.

The STMicroelectronics team was also facing the same issue. This blog post explores how the team verified a 10BASE-T1S automotive ethernet subsystem using a Cadence tools-based multi-platform verification, which unifies simulation, emulation, and formal verification techniques. At CadenceLIVE Silicon Valley 2026, the STMicroelectronics team showed how this approach improved functional coverage by 15% and reduced verification cycle time by 40% versus a simulation-centric flow.

Why 10BASE-T1S Matters in Automotive Networks

Traditional in-vehicle networks have relied on buses such as CAN, CAN FD, LIN, and FlexRay. Each served an important role, but together they added complexity. ECUs often had to support multiple bus types, software stacks became harder to manage, and additional wiring and connectors increased system weight and potential points of failure.

10BASE-T1S changes that equation. It enables automotive ethernet over a twisted-pair copper connection and supports multidrop network topologies.

In the STMicroelectronics presentation, one of the central advantages was the ability to reduce the number of bus interfaces an ECU must support while also reducing wiring complexity. The optional power-over-data-line capability further strengthens the value proposition by allowing the same cable to carry both data and power where applicable.

A key technical feature is physical layer collision avoidance (PLCA), and provides a collision free access on a shared bus.

 PLCA provides deterministic access to each node and ensures that it uses the entire 10 Mbps bandwidth. The working principle of PLCA is that transmit opportunities on a mixing segment are granted in sequence based on a node ID unique to the local collision domain (set by the management entity). Each node gets a fair opportunity to transmit, and each transmission is completed before the next node takes the bus. This creates the deterministic, collision-free behavior required for shared-bus automotive communication.

The Verification Challenge: New Protocol, Complex SoC, No Room for Surprises

For STMicroelectronics, the challenge was not simply verifying an ethernet block in isolation. The subsystem sat inside a broader SoC context with multiple CPU groups, multiple cores, AXI masters, memories, a network-on-chip, bus-width adaptation logic, and multiple Ethernet-related paths. Ethernet traffic moved through the NOC, into memory, and ultimately toward CPU processing. That system context made end-to-end behavior just as important as protocol correctness. The team faced three core challenges.

• The 10BASE-T1S, PLCA, and three-pin interface specifications are relatively new and still evolving. With several gray areas, the team had to rely on best practices and close collaboration to interpret the spec consistently.
• As multiple clocks, multiple CPU cores, several ethernet instances, and multidrop scenarios all had to work together, verifying collision-free communication across a shared bus added another layer of difficulty.
• Simulation alone is not enough. The sheer breadth of scenarios, from functional checks to performance under heavy traffic to precise timing, demanded more than a single verification engine could deliver efficiently.

These challenges called for a structured, multi-platform verification strategy rather than a simulation-centric approach.

A Multi-Platform Verification Methodology

To address these challenges and uphold the "no surprises, later in silicon" objective, the STMicroelectronics team implemented a multi-platform flow leveraging Cadence tools. This platform used ethernet verification IP for simulation, Palladium for emulation, and formal verification.

• Cadence Ethernet VIP for comprehensive functional level verification
• Palladium-based emulation for SoC scenarios and performance scenarios
• Formal verification is employed to verify ED pulses and timing-related checks

This combined methodology provides detailed protocol-level control and debugging, enables large-scale SoC and software scenario testing via emulation, and delivers precise timing assurance through formal methods. Collectively, these platforms offer a holistic view of the subsystem, surpassing the capabilities of any single engineering approach.

Cadence Ethernet VIP also played a central role in accelerating the verification environment, reducing the time to almost a week compared to a month during the first project's bring-up. That improvement reflected both methodology reuse and close collaboration between STMicroelectronics and Cadence around protocol interpretation, VIP integration, and feature enablement for areas such as PLCA and multidrop operation.

Coverage-Driven Verification Across Engines

A critical strength of the flow was coverage continuity.

 Cadence Ethernet VIP provided built-in monitors, checkers, and coverage, including instance-based functional coverage that could be extended by the user. This was important because the design included multiple Ethernet nodes, and future designs could scale even more Ethernet instances. Instance-based coverage helped the team understand progress at the node level rather than only at the aggregate level.

The team verified register access, frame transmission and reception, reset and configuration commands, half-duplex operation, PLCA mode, multidrop scenarios, low-power behavior, and sleep commands.

In the simulation, more than 40 directed and random tests were used for IP verification. In emulation, the team exercised stressed multi-frame scenarios and performance-oriented cases. In formal, assertions were used to verify the ED pulse width and timing behavior.

Key Metrics: Earlier Bug Discovery and Stronger Silicon Confidence

The outcome was measurable, and the results tell a clear story. STMicroelectronics reported 97.2% toggle coverage, 94% code coverage, 90% branch coverage, and 95% coverage for PLCA and three-pin specific bins in functional coverage. The team also achieved nearly 100% toggle coverage at the SoC level in the formal context described in the presentation.

Just as important, the flow helped find issues early in the SoC verification process. By applying the right engine to the right class of problem, VIP-based simulation for functional behavior, Palladium emulation for software-driven and performance stress, and formal verification for precise timing checks, the team improved confidence before tapeout and avoided silicon respins.

The Takeaway

STMicroelectronics’ CadenceLIVE Silicon Valley presentation showed a practical path for verifying a new class of automotive Ethernet subsystem. 10BASE-T1S offers significant system advantages for in-vehicle networking, but it also introduces verification requirements spanning protocol behavior, SoC integration, multidrop arbitration, software-driven traffic, and timing-sensitive interface checks.

By using Cadence Ethernet VIP, Palladium emulation, and formal verification in a coordinated multi-platform flow, STMicroelectronics accelerated bring-up, improved coverage, exposed issues earlier, and moved toward silicon with greater confidence. For automotive design teams facing the next generation of Ethernet-based in-vehicle networking, that is the real value of multi-platform verification is fewer gaps, faster learning, and fewer surprises in silicon.

Want to learn how STMicroelectronics achieved these results? Watch the full CadenceLIVE Silicon Valley 2026 presentation, “From Protocol to Silicon: Multiplatform Verification of 10BASE-T1S in Automotive Ethernet SoCs” by Bipul Haldar, Asjad Fahmi, Sahana Sanagowda from STMicroelectronics, and Krunal Patel from Cadence.