Xilinx SoC FPGAs Ideal Fit For OVM and MDV

Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009).  In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of logic, but the high-end SoCs -- represented by product families such as the Xilinx(R) Virtex(R)-6 and Spartan(R)-6 -- are growing fast.  That is exactly the type of design we've targeted with the Incisive Enterprise Verification solution and the OVM.

Cadence and Xilinx are working to simplify the development of these complex SoCs by applying the Incisive solution to the newly announced Xilinx Targeted Design Platforms. There are two significant parts of the announcement -- collaboration around new, high-performance, standards-based simulation libraries and application of the OVM for SoC FPGAs.

The first point represents significant engineering work to move away from the proprietary packaging that Xilinx used to the new IEEE standard encryption championed by Cadence.  The new encryption standard was originally donated by Cadence and is now part of the SystemVerilog (1800), Verilog (1364), and VHDL (1076) standards. Cadence chairs this standards effort and was able to help Xilinx adopt the technology and prove it in common customers.  The result is an average 2X speed-up for simulation, with some users experiencing still higher performance.  Watch this blog for a team genIES explanation of this compelling new standard.

The second, and possibly more significant, point is the recognition that the OVM is an ideal choice for SoC FPGAs. These FPGAs typically depend on standard protocols -- on-chip bus and interface protocols -- and reuse of both vendor-supplied and user-created VIP. Furthermore, these FPGAs are scaling to the point where users need to break with the traditional "burn-and-churn" FPGA methodology and adopt the more comprehensive, metric-driven methodology applied to ASICs of the same size and complexity.

For all of you who have been looking for more FPGA verification content from Cadence, look at this announcement as just the first with more to come.  If you have any requests in the FPGA space, please feel free to comment here or contact me at asherer@cadence.com.

=Adam Sheriblog