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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

TLM Design and Verification: What to See at DAC This Year

If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San…

• 1 min read
High-Level Synthesis , DAC , TLM , C to Silicon , transaction level , tlm verification , System Design and Verification , TLM design , embedded software , ESLsyn , C-to-Silicon , SystemC , HLS , NASCUG , ESL

Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform

There are two choices for how to handle USB devices in a virtual platform. A USB…

• 4 min read
Virtual System Platform , virtual platforms , virtual prototypes , embedded software , USB , Zync-7000 , SystemC , physical USB devices , xilinx , linux , QEMU , System Design and Verification

Tips on Writing Macros in Specman e Language

In this blog, I will present some tips that can be very useful when you write e macros…

• 4 min read
AF , Specman , Functional Verification , Incisive , e language , define-as , writing macros , macros , testbench , simulation , verification

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

We in product management are often accused of jumping the gun and announcing products…

• 5 min read
DAC , CDNLive , Acceleration , debug , Functional Verification , AMD , System Development Suite , Incisive , in-circuit emulation , Palladium XP , Emulation , in-circuit acceleration , Design Automation Conference , DAC breakfast , System Design and Verification

The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include…

• 4 min read
AVIP , SystemVerilog , accelerated VIP , Verification IP , uvm , Acceleration , Functional Verification , VIP , Palladium , Palladium XP , Emulation , VIP Catalog , simulation VIP , ACE verification , e language , SCE-MI , SystemC , protocol verification , simulation , verification

American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working…

I think all of us engineers have faced at one point or another the need to explain…

• 2 min read
Rapid Protoytping Platform , Virtual System Platform , virtual platforms , awards , Watson , virtual prototypes , American Technology Awards , Jeopardy , System Development Suite , VSP , Incisive , Palladium XP , Raritan , Mother's Day , System Design and Verification , cloud computing , FPGA-based prototyping

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA…

• 2 min read
DAC , Incisive Formal Verifier , ABV , Functional Verification , Formal Analysis , formal , "Coverage Unreachability" , coverage unreachability , formal apps , model checking , bypass verification , apps , Lego , User Track , assertions , papers , DAC 2012 , robot , IEV , Design Automation Conference , Rubik's Cube , IFV , Assertion-based verification

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage…

Memory management is not something the Specman user is supposed to worry about. Nobody…

• 9 min read
AF , Specman , Memory , garbage , Functional Verification , garbage collection , Specman garbage collection , Incisive , e language , managing memory , Specman data , memory errors , testbench , simulation , memory management , verification

Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal…

This 6 minute video is a quick overview of our formal scoreboard app. Specifically…

• less than a min read
scoreboard , ABV , Joerg Mueller , Formal Analysis , formal , video , formal apps , apps , formal scoreboard , IEV , IFV

Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

In my last blog post , I covered three frequently asked questions about using the…

• 5 min read
taskset , virtual platforms , Unity 2D , System Development Suite , embedded software , VSP , Ubuntu , VirtualBox , virtual prototype , Virtual Machine , Linux vs VirtualBox , Unity3D , xilinx , graphics , linux , Zynq-7000 , simulation , ESL , System Design and Verification

Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition

The use of virtual machine technology offers great ease of use benefits. Since the…

• 7 min read
VBoxManage , port forwarding , network address translation , eclipse , virtual platforms , NAT , virtual prototypes , embedded software , Xilinx SDK , Ubuntu , VirtualBox , system design , Virtual Machine , FAQ , System Design & Verification , xilinx , Zynq virtual platform , Zynq-7000 , ESL

My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!

The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation…

• 4 min read
AF , IntelliGen , Specman , debug , Functional Verification , Gen debugger , test generation , Gen , Generation , e language , Constraints , constraint not enforced , verification

Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a…

• 8 min read
AF , SystemVerilog , Specman , OVM ML , Functional Verification , Testbench simulation , OVM e , EDA , e , stack trace , Signal Integrity , e language , team specman , Aspect Oriented Programming , eRM , specman crashes , simulation , AOP , IES-XL

Video: “Drive For Innovation” Finds It At Every Turn

With some notable exceptions, too often technology trade press reporting has been…

• less than a min read
Brian Fuller , Avenet Express , Joe Hupcey III , innovation , "Drive for Innovation" , UBM Electronics , Chevy Volt , EE Times

Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded…

• 3 min read
zynq , Memory , virtual platforms , TLM , virtual prototypes , SDRAM , Verilog , SystemC memories , SystemC , memory models , modeling memories , linux

Lessons from CDNLive! India Best Paper -- Property Driven Simulation in IEV

Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification…

• 2 min read
ABV , CDNLive India , Vinaya Singh , Formal Analysis , NVIDIA , ADS , property-driven simulation , CDNLive! , IEV , Assertion-Driven Simulation , Formal verification , India , Assertion-based verification

Trying to Make Sense of the Chaos – Impressions from Design West 2012

Walking the show floor of "Design West," the show formerly known as "Embedded Systems…

• 3 min read
SysML , Intel , Embedded Systems Conferences , software development tools , chaos , OS , embedded software , UML , Test , Design West , software , ARM , embedded systems , operating systems

Video: PSL and SVA for SPICE – Yes, Assertion Based Verification (ABV) for Analog…

In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background…

• less than a min read
Joe Hupcey III , ABV , video , SVA , Virtuoso , PSL , DVcon , assertions , Don O'Riordan , SPICE

CDNLive Silicon Valley 2012: Much More than Moore

Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley…

• 3 min read
ARM Techcon , uvm , Joe Hupcey III , ABV , CDNLive , metric driven verification (MDV) , TSMC , Lip-Bu Tan , UVM ML , apps , Lego , assertions , CDNLive! , robot , CDNLive Silicon Valley , ARM , Rubik's Cube , IFV

Video: Oski Dares You to Challenge Their Formal & Assertion-Based Verification Skills…

I've seen a lot of intriguing promotions over the years, but at DAC 2012 June 3-7…

• less than a min read
DAC , Joe Hupcey III , ABV , Formal Analysis , formal , Vigyan Singhal , Oski Technology , IEV

Photo Essay, Video Playlist, and Comments on DVCon 2012

In addition to the annotated image gallery (click here or on the image), or the playlist…

• 3 min read
NextOp , uvm , Low Power , Joe Hupcey III , ABV , videos , Yunshan Zhu , Functional Verification , Formal Analysis , ABVIP , video , formal apps , Vigyan Singhal , Chris Komar , Oski Technology , UCIS , DVcon , assertion synthesis , robot , Assertion-Driven Simulation , Formal verification , Assertion-based verification

DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Ap…

In this interview Product Engineer Chris Komar recaps the tutorial on formal apps…

• less than a min read
Low Power , Joe Hupcey III , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , formal apps , Chris Komar , DVcon , apps , assertion synthesis , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Differentiation Through Hardware is Not Going Away

Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design…

• 5 min read
High-Level Synthesis , 4G , TLM , hardware , android , system realization , hardware-dependent software , SoC , sub-systems , Quad-HD , iOS , software , DVcon , SystemC , smartphones , tablets

Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17th North American SystemC User Group meeting ( NASCUG ), will take place this…

• 3 min read
IP , zynq , virtual platforms , TLM , platform , virtual prototypes , fixed sub-systems , sub-systems , Tensilica , subsystems , OMAP , DVcon , SystemC , xilinx , NASCUG , FPGA , System Design and Verification , verification

Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has…

• less than a min read
performance , SystemVerilog , Multi-Core , Incisive , Funcional Verification , Incisive Enterprise Simulator (IES) , IES , IES-XL

Using a Linaro File System on the Cadence Virtual Platform for the Xilinx Zynq-7000…

Linaro has emerged as a great place to find well tested toolchains, Linux kernels…

• 3 min read

DVCon 2012 Preview: Focus on Formal & ABV Events and Papers

In a few short weeks DVCon 2012 will be upon us ( Feb. 27 - March 1 in San Jose …

• 2 min read
Joe Hupcey III , ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , Bin Ju , video , tutorial , Facebook , Chris Komar , DVcon , apps , assertion synthesis , assertions , robot , IEV , Assertion-Driven Simulation , Darrow Chu , Formal verification , IFV , Assertion-based verification

The Zynq Virtual Platform: Not Just for Pre-Silicon

One of the biggest misconceptions about Virtual Platforms is that they are only useful…

• 4 min read
Virtual System Platform , zynq , virtual platforms , Zynq-7000' , pre-silicon , virtual prototypes , post-silicon , embedded software , Watchdog Timer , SystemC , linux
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