Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
If you’re reading this, you must have heard about the M-PCIe specification that has just been announced by two very important standardization bodies in the semiconductor industry—MIPI Alliance and PCI-SIG. According to the press release that was released during the PCI-SIG event last month, “M-PCIe specification provides uncompromised scalable performance while delivering a consistent user experience across multiple mobile platforms.” This sounds very appealing, but exactly does it mean to the mobile SoC developers?
As I wrote in my previous post, the MIPI Alliance is known for the introduction of over 30 specifications targeted for mobile platforms, and has managed to do this in just 10 years. Certainly, 10 years is a lot of time, and mobile market is the fastest growing segment of the semiconductor industry, but still the number is impressive. Even more impressive is the fact that these specs have been adopted by the major players in the market, and thus have made their way into pretty much every mobile device there is.
PCI-SIG, on the other hand, is very conservative when it comes to giving birth to a new child. Actually, they have been active for twice as long as MIPI and developed 10 times fewer specifications than their latest partner. But don’t let this unfavorable comparison fool you. The money in the PCI business is still far more than in the all MIPI Alliance specifications combined, mostly thanks to the wide adoption of the PCI, and later PCI Express bus in the infrastructure, storage, and PC markets.
This clash of the titans of their domains sends a very important message to the whole semiconductor market. It shows how much convergence there is between mobile and infrastructure, and the direction is now to take advantage of this fact. Actually, key players in both markets have been observing each other for quite some time, and actions have already been taken. ARM and Intel are perfect examples here, with ARM’s A57 targeted also for server architecture and Intel’s Atom processors implemented in mobile devices. While there is little chance of these two joining forces, there also are no obstacles for the standardization bodies coming from different worlds to create a synergy effect.
World premiere of the first native M-PCIe controller by Cadence at the MIPI Alliance event on 18 June.
For design IP providers, M-PCIe is a perfect opportunity to deliver to market a solution that has the best of both worlds, and to become ambassadors for the new technology. It’s no secret Intel is the founding father of the PCI architecture, and Qualcomm keeps the MIPI Alliance going strong.
Design IP leaders like Cadence and Synopsys already have solutions on M-PCIe. Cadence showed their demo on 18 June, at the MIPI Alliance Demo Day in Warsaw, Poland, while Synopsys demonstrated the IP a week later, at the PCI-SIG conference. This sequence actually makes Cadence the first company to reveal a working M-PCIe solution, and contrasts with the statement made by other IP providers recently. Also, I’ve just learned that only the Cadence solution is a native M-PCIe controller that runs without any “regular” PCI conversion layers in between.
Martin James of Cadence at the PCI-SIG Developers Conference, where M-PCIe was announced.
Altogether, the engagement from the standardization bodies, major chip manufacturing companies, and design IP leaders makes the M-PCIe the standard to watch. For SoC companies, M-PCIe is definitely something that they want to give a thought to before they leave for well-deserved holidays. Definitely better before than after.