Tensilica, Design, and Verification IP Blogs

The 21^st European Test Symposium (IEEE EST) took place in Amsterdam (Netherlands) from May 23^rd-27^th. With all the ideas and challenges in designing applications and with new trends in the area of electronic-based circuits and system testing, it was good to focus on some of the other important topics of achieving system success and a future-proofed design. And Cadence had the SerDes experience to share.

The presentation was given a title ‘Augmenting Testability in Mixed-signal SerDes IP through IEEE 1687-Compliant DFT Ecosystem’ and has been presented by an international team of Cadence specialists:

• Vladimir Zivkovic (Cadence United Kingdom)
• John Vogel (Cadence United States)
• Rajesh Khurana (Cadence India)
• Scott Shelton, Daniel Cohen (Cadence United States)
• Colin Scott (Cadence United Kingdom)
• Vivek Chickermane (Cadence United States)
• Krishna Chakravadhanula (Cadence United States).

In the talk, the team discussed augmenting testability in mixed-signal SerDeS IP through IEEE 1687-complaiant DFT ecosystem. Our silicon-proven 16Gbps PHY is available in 16nm with smaller nodes in development. With multi-protocol support (PCIe 4.0, USB 3.1, SATA 3.3, 10G-KR, XAUI/RXAUI, Q/SGMII) and multi-link configurability, it proves useful to the most demanding architects and designers. Easily able to support a different protocol in each lane and future proof design, Cadence 16Gbps PHY helps customers easily adapt to unanticipated market requirements. More so, our SerDes IP can be set-up to interact with a chip on a test-board using a PC or USB-JTAG cable. IPs can also be controlled using a sequence of JTAG Reades/Writes.

Figure 1: 16Gbps Multi-Link, Multi-Protocol SerDes

One of our priorities is not only the innovation itself and the quality of the product but the intention of helping customers with these very difficult system challenges. That’s why Cadence is incorporating the IEEE 1687 standard, which facilitates an easier SoC integration and testing process. With highly reusable DFT infrastructure and other important features, the 16Gbps PHY meets the testability needs of highly complex SoCs.

And since we’re talking about trends – European Test Symposium raised visibility into the formation of a user group around analog fault simulation and 1687 extension towards analog ports and parameters. It includes Intel, AMD, NXP, On-Semiconductors, Infineon, and others.

For more information and exciting announcements from the event, please visit the official page for IEEE ETS 2016 here.