An inconvenient truth about using DDR3 SDRAM for embedded designs

DDR (double data rate) memory chips mounted on DIMMs have long been the mainstay of the PC and server industries. The resulting sales volumes often make these DIMMs the best value available today in terms of cost per bit. PC DIMMs have been 64 bits wide through all DDR generations from the original DDR (also called DDR1) parts to today’s DDR3 chips. Many embedded designs also use PC DIMMs because their high sales volumes make them a relatively cheap source of high-capacity DRAM. However, DDR3 memories have one key characteristic that may make 64-bit DDR3 DIMMs a poor choice for many embedded designs: DDR3 SDRAMs use an 8n prefetch architecture (eight bits fetched or stored in parallel from the memory array per DDR3 data pin) to keep pace with ever-escalating RAM capacity and memory transfer rates while keeping memory bit-cell access speeds and cycle times reasonable. As a result, DDR3 SDRAMs only support 8-beat data bursts so DDR3 chips integrated into PC DIMMs with 64-bit word widths will transfer 64 bytes per data burst. While 64-bit DDR3 DIMMs match up well to microprocessors with 64-byte cache-line buffers, they do not work very well with microprocessors that have 32-byte cache-line buffers and many embedded processors still employ such buffers.

Burst-length options for SDRAMs decrease with each new SDRAM generation as memory-chip capacity has become larger and as transfer rates climb--both of these trends drive the need for larger and larger prefetches within the SDRAM’s on-chip memory array. The first SDR (single data rate) SDRAMs could support four data-burst lengths: 1, 2, 4, and 8 beats. First-generation DDR SDRAMs support three burst lengths: 2, 4, and 8 beats. DDR2 SDRAMs support only two burst lengths: 4 or 8 beats. DDR3 SDRAMs only support 8-beat bursts. Consequently, DDR3 DIMMs with their 64-bit data width and 8-beat bursts will transfer 64 bytes per data burst.

But wait, you say. Isn’t there a burst-chop feature in DDR3 that cuts the data burst to 4 beats. Yes, that’s correct. A DDR3 BC4 burst chop will essentially mask the last 4 bits of the burst thus reducing the number of clocks needed for Read-to-Write, certain Write-to-Read, and certain Write-to-Precharge transitions within the DDR3 state space. However, back-to-back reads and writes (Read-to-Read or Write-to-Write transitions) must always employ BL8 timing resulting in no clock-cycle reduction even when DDR3’s burst chop is used. Even the transactions that benefit from BC4 timing will still run into tRC and tFAW timing restrictions that further limit DDR3 performance. All of these factors mean that using DDR3’s burst-chop mode greatly complicates control of DDR3 memory and the limited performance gains made at the cost of greatly complicated memory control make effective use of DDR3’s burst chop mode fairly impractical.

So in reality, there are only three good solutions to the problem of DDR3’s 8-beat data bursts for embedded (non-PC, non-server) designs:

1. Don’t use 64-bit DDR3 DIMMs for embedded processors that have 32-byte cache-line buffers. Instead, use individual DDR3 SDRAM chips organized in a 32-bit configuration if DDR3 SDRAM turns out to be the best way for you to meet cost and performance design goals for the memory subsystem.

2. Use DDR2 or LPDDR2 memory or an even older generation of SDRAM if you can meet your performance and economic design goals this way. However, keep in mind that older DDR memories tend to rise in price over time as their popularity, sales volumes, and availability decrease.

3. Pick an embedded processor with a 64-byte cache line buffer and then go ahead and use DDR3 DIMMs.

It’s also a really good idea to design the SDRAM controller and PHY to work with multiple SDRAM generations, as discussed in this blog previously. (See the description of ST Microelectronic’s SPEAr1300 embedded processor, http://j.mp/crUOBg, for an example.)

As long as PC and server sales consume the bulk of the SDRAMs manufactured--because each PC and server tends to use a lot more SDRAM than most embedded designs--the memory requirements of the relatively few PC and server processors will continue to outweigh the needs of the embedded processors in the much larger annual unit sales of mobile and embedded products when memory vendors determine what SDRAM features they will provide to the market. Your job as a system designer is to deal with the realities of the memory market and optimize your embedded design accordingly.