Tensilica and Design IP Blogs

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision systems, digital noise reduction, and advanced driver assistance systems (ADAS), look at Cadence for the key IP to speed your design effort.

We just announced that we have collaborated with a major foundry to produce an IP portfolio that’s ASIL-B ready and ASIL-C/D capable. See the press release for full details. Cadence IP is area- and power-optimized for the AEC-Q100 Grade 2 temperature range, eliminating the need to carry Grade 1 power and area penalties into cost-sensitive automotive SoC designs. 

Our automotive IP portfolio includes:

• 4266-speed grade LPDDR4/4X DDR PHY and controllers
• PCIe 4.0/3.0 PHY and controllers
• MIPI D-PHY subsystem
• USB 3.1/2.0 subsystems
• DisplayPort subsystem
• UFS subsystem
• Octal SPI/QSPI subsystem
• Gigabit Ethernet subsystem with TSN (time-sensitive network, a requirement in automotive Ethernet)

Paul McLellan wrote an excellent blog about the multi-level approach required for designing automotive systems. It’s recommended reading for anyone seriously interested in automotive electronics.