Cadence ONFI 4.0 Flash Memory IP Increases Data Access to 800Mtps and Reduces Power Up to 50%

10 Aug 2015 • 2 minute read

Announcing Availability of ONFI 4.0 IP

Flash memory applications have expanded from USB Flash Drive “sticks” to solid state drives (SSD) and beyond, as designers demand increased non-volatile storage capacity and performance. Designers are also faced with the challenge to reduce system-level power. To meet these needs Cadence is unveiling its Open NAND Flash Interface (ONFI) 4.0 IP, delivering increased data access rates up to 800 MegaTransfers/sec (Mtps) and reducing power consumption more than 50%.

The ONFI 4.0 specification was published in April of 2014 by the Open NAND Flash Interface organization. The standard includes the evolutionary NV-DDR3 interface that utilizes reduced voltage for higher performance and improved power consumption. Performance for NV-DDDR and NV-DDR3 I/O scales to 667Mtps and 800Mtps, and power consumption is reduced to >50%.

The Cadence ONFI 4.0 IP also includes an innovative architecture which offers options for parallelized error correction code (ECC) logic that supports programmable correction of up to 128 errors while minimizing additional area or latency of the implementation. The ONFI 4.0 IP is the latest extension of Cadence’s comprehensive Flash Memory IP Portfolio, which includes support for Secure Digital (SD), Embedded MultiMedia Card (eMMC), and Quad Serial Peripheral Interface (QSPI).

The IP combines architectural influences from Cadence’ ONFI 3.0 IP, along with an innovative implementation of the BCH logic. The design provides programmable error correction that can simultaneously handle up to 128 errors, without incurring large area and latency costs. The proprietary parallel computational approach implementation enables the architect to select more error correction with minimized incremental area and latency from the computation.

New Quad Serial Peripheral Interface (QSPI) IP

Cadence offer QSPI IP for systems that need access to reliable NOR flash devices to enable such operations as system boot.The demand for faster boot times are being addressed by higher performance QSPI devices, which can lead to more challenging system design.To help alleviate some of the system-level timing challenges with higher data rate QSPI, Cadence has developed QSPI Interface IP that leverages an embedded Soft PHY. The Soft PHY includes a digital delay line (DDL) which enables more accuracy in generating the strobe to capture and launch data between the SoC and QSPI device as compared with the traditional approach of using a 4x fixed clock which may not balance set up and hold times of the transmitted data.

Secure Digital (SD) and Embedded Multimedia Card (eMMC) IP

Cadence is also extending its support for SD and eMMC host controller IP with the availability of SD4, which can support data rates up to 312MBps, and eMMC5, which supports data rates up to 400MBps.

Verification model support

Cadence also offers full Verification IP models that support ONFi (3.x to 4.4), SDcard (from 2.0 to 4.0), eMMC (through 4.0), and QSPI. The combination of Verification IP and Design IP provide complete solutions for these leading protocols.

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