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Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since then, our PCIe offerings have evolved to include the lowest power PHY solutions available, FPGA platforms for prototyping, software drivers, and the industry’s leading verification IP.
Compliance: Last year, the PCI-SIG began official Gen3 compliance testing. The Cadence PCIe controller achieved Gen3 compliance in 2013. In March 2014, we achieved compliance with our Gen3 controller using a Cadence platform using FPGAs and our Gen3 PHY chip. This was an industry first, with a Gen3 controller IP synthesized to an FPGA performing at 8GT/s rates.
The Cadence FPGA platforms, known as Rapid IP Evaluation Platforms (RIPE), are available for customers to prototype and evaluate their solutions using Cadence controllers and hard IP. These platforms are designed to allow various Cadence controllers and PHYs to be tested on a common platform. We demonstrated this platform at the recent PCI Developers Conference in Santa Clara.
Configurable: The Cadence PCIe controller (soft IP) is used widely in the industry, in applications ranging from the most popular gaming consoles to high-performance RAID controllers to supercomputing applications. The Cadence PCIe PHY has been adopted in a wide range of platforms, from mobile phones to storage and networking applications. This IP is designed to be highly configurable and is fully verified in the target configuration – a methodology that is unmatched in the industry.
Low Power: The Cadence PCIe PHY and controller provide support for the latest low-power ECNs, including the L1-substates with CLKREQ (link here, available only to PCI-SIG members). While low-power states are traditionally associated with lengthy transition times to active states, the Cadence solutions apply innovative techniques that reduce these transition times dramatically, while providing significant power savings.
Cadence has a short video on low-power PCIe solutions on its Whiteboard Wednesdays site.