Cadence Ports LPDDR4/DDR4 Combo PHY to TSMC 28HPC to Serve Rapid Adoption in Consumer Products

Rapid consumer product revolution continues to be enabled by semiconductor technology innovation. Driven by Moore’s Law, memory capacity increases, memory access rates, and single chip integration leads to new capabilities, merging of functionality, and increased battery life. Consumer products are fast followers of leading edge electronics such as smart phones and networking infrastructure. We consumers are cost-sensitive, so we wait for these capabilities to cross our personal price thresholds.

Figure 1 – Leading Consumer Products

Cadence has completed a tapeout and customer delivery of our leading edge LPDDR4/DDR4 memory interface IP, ported to the TSMC 28HPC process. Originally announced at Memcon 2014, and developed for TSMC 16FF+, this IP has been selected by multiple customers for their mobile applications. Read about how that IP has been demonstrated running at 3200Mbps here.

Adoption of this process node continues to grow, with an increasing number of consumer SoC design starts. This seems to be due to its affordability, reliability, performance, and power consumption characteristics. The flexibility of the combo LPDDR4/DDR4 IP helps customer maximize their performance and minimize system BOM costs.

In addition to providing flexibility between DDR4 and LPDDR4, the Combo PHY provides flexibility to minimize system cost as the memory market ramps up availability of DDR4/LPDDR4 memory chips. The memory market is not yet supplying adequate volume of LPDDR4. So many SoCs are being designed today for LPDDR4 and LPDDR3 as well as DDR4 and DDR3 to future proof the design, and be ready to jump to the appropriate protocol to meet their system performance and cost requirements as the DRAM market evolves. This is a similar dynamic to what happened with DDR3 to DDR4 this time adding LPDDR3 and LPDDR4 in the mix.

Come see the DDR4 testchip in action at Memcon in the Cadence booth.