CDNLive IP Track Presentations Available Online

8 Apr 2015 • 2 minute read

With more than 100 presentations, live product demos, designer expo, and numerous engaging technology discussions, CDNLive Silicon Valley 2015 was a networking opportunity worth joining. And since conference proceedings from all 10 technical tracks are now available online, we wanted to share with you once more all the inspiring design, verification and processor IP presentations in this year’s IP track.

Best IP Paper Recognition

One of the Best Paper Awards went to Dinesh Venkatachalam from Broadcom who gave a presentation on “External Memory Architectural Choices for Terabit-Class Devices.”

Dinesh presented in-depth information not only about existing solutions, including terabit-class devices, standard and graphic memories, but also about emerging standards such as high-bandwidth memory (HBM) or hybrid memory cube (HMC). The entire presentation is available here.

Design, Verification, and Processor IP Track

And here’s what was presented by speakers from Cadence, IPextreme, and Broadcom for the design, verification, and processor IP track:

Bringing PCIe Performance to Mobile Platforms – Shri Jaganathan, Cadence
Rethinking SoC Architecture for the IoT Age – Christopher Rowen, Cadence
Programmable, Low Energy Embedded Vision for Next Generation Wearables and Mobile Application - Pulin Desai, Cadence
Applying Maslow’s Hierarchy of Needs to IP Reuse – Warren Savage, IPextreme
Achieving the Lowest-Power Processing in Always-On Applications – Larry Przywara, Cadence
Simulation and Modeling of DDR4 Memory Interface and Interposer Test Fixtures Using S-param – Philip Pun, Cadence
External Memory Architectural Choices for Terabit Class Devices – Dinesh Venkatachalam, Broadcom
DDR4 Subsystem Implementation on 16FF/16FF+ Targeting Infrastructure Applications – Challenges and Design Techniques – Anurag Jain, Cadence
Design Considerations for LPDDR4/3 PHY and Controller Sub-System – Kishore Kasamsetty, Cadence
Automated Performance Verification of Multi-Core SoCs with Layered Interconnect Fabrics – Arindam Guha, Cadence
LPDDR4 - It is not just for Mobile Anymore – Luigi Ternullo, Cadence

You can access all the above presentations by visiting our CDNLive Proceedings page.

So what’s next?

CDNLive Silicon Valley was the first of nine CDNLive conferences that will be held all around the world this year. The next one will take place April 27 in Munich, Germany. And we really hope to see you at the CDNLive EMEA 2015 conference!

And Design Automation Conference is just around the corner on June 8-11 at Moscone Center in San Francisco. Cadence will have a strong IP presence there again this year, with increased opportunities for customer engineers to engage our IP engineering team.

Steven Brown

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