DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps

Back in October we announced the TSMC 28HPC tapeout of our DDR/LPDDR 4/3 Combo PHY. Since then we have made great progress with customers, and our own silicon bring up. Most recently, the combo PHY IP is brought up in our lab and running at 2400 Mbps.

Many price sensitive consumer products continue to leverage 28nm technology for affordable high performance and low power consumption. Originally announced at Memcon 2014, and developed for TSMC 16FF+, this IP has been selected by multiple customers for their mobile and enterprise server/networking applications. Read about how that IP has been demonstrated running at 3200Mbps here.

As the memory market ramps up supply of LPDDR4, this combo IP gives our customers the flexibility to build one design, and optimize overall system cost with that supply growth. This is particularly important for the cost-sensitive consumer products market segment. This particular DDR/LPDDR 4/3 combo PHY is ideal for customers who want to build-in both protocols for flexibility to match DRAM supply for these protocols to minimize system cost. This is Cadence’ first DDR/LPDDR combo PHY in 28HPC silicon, and the IP in LPDDR4 mode is already demonstrated passing BIST at 2400 Mbps. The data eye exceeds the JEDEC timing window requirements for setup and hold parameters across all protocols.

Figure 1 – Eye Diagram of LPDDR4 operating at 2400 Mbps

There are several customer projects in flight (ex - SSD application, tablet application, video camera application), using DDR4, LPDDR4, and the DDR/LPDDR 4/3 combo configurations. The IP is available now for early partners. Silicon characterized general availability of the IP is planned for April 2016.

Read more about Cadence DDR PHY IP here. Contact us to learn more details of our 28HPC plans and development status.