Denali to demo new PureSpec 2.0 verification-management technology at DAC 2010

This news is a bit far afield for Denali’s Memory Blog, but many of our blog readers are deeply involved in verification. Next week at DAC in Booth 1183, Denali will be demonstrating a huge leap forward in verification-management technology with early previews of its PureSpec 2.0 tool. Because of its leading presence in verification IP (VIP), Denali is actively involved in verification flows. Working with customers on the many issues that crop up during verification of complex chip designs, Denali’s VIP development teams have learned what’s needed to improve testplan effectiveness. It’s become apparent that configurable VIP can do a lot to push the boundaries of automated verification and PureSpec 2.0 is Denali’s approach to realizing that potential. Consequently, Denali’s engineering team is creating a new class of verification management tools capable of exploiting VIP configurability by more fully automating the development and management of verification testplans. The resulting technology is called PureSpec 2.0.

In addition to the tools needed to harness VIP configurability for automated verification, PureSpec 2.0 technology includes an Explorer GUI tool that permits far more intuitive debugging by making it easy to look at the verification data that the VIP is already collecting. For example, in applications with packet processing, the Explorer GUI provides much easier access to queue states, information about the packets held in the queues, and error status. The PureSpec 2.0 Explorer GUI also permits visualization of queue use and FSM state.

The purpose of this new verification-management technology is to permit better, faster top-down debugging. The Explorer GUI provides verification engineers with the ability to zoom in on events of interest and to closely examine object details such as errors and transaction events on a cycle-by-cycle basis. In essence, this technology gives the verification engineer the equivalent power of a high-end logic analyzer, but for simulations rather than hardware.

At this point, PureSpec 2.0 is a technology demonstration, but if you’d like an early look at this new verification-management technology, please come to Denali’s booth at DAC, #1183.