Tensilica, Design, and Verification IP Blogs

We have an exciting Design IP track at CDNLive Silicon Valley again this year. ARM, Mellanox, Broadcom, and Hardent talk about important IP technology topics. And Cadence will be sharing some of the latest about our technology development.

Take a look at the full agenda—and don't miss the Design IP track (track 11) on Wednesday!

The Design IP track is comprised of: 

• DES201: Dinesh Venkatachalam, Broadcom—"SerDes 101 for SoC Designers"
• DES202: Gilad Shainer, Mellanox—"PCIe 4 Interoperability Testing with Mellanox"
• DES203: Alain Legault, Hardent—"VESA Display Stream Compression: Taking interface IPs to the next level to create higher resolution displays in consumer electronics"
• DES206: Mike Eftimakis, ARM—"Designing IoT Products Cheaper and Faster"
• DES205: Michal Staworko, Cadence—"Challenges of a Complete USB Type-C Subsystem Implementation in a Chromebook Applications Processor"
• DES204: Amjad Qureshi, Cadence—"Complexities in Developing a High-Performance DDR Subsystem at 3200Mbps on 16FF+"
• DES207: Prashanth Thota, Tektronix —"How to Efficiently Design and Electrically Validate a DDR4 Interface"

There are also Cadence Design IP presentations in other tracks at CDNLive Silicon Valley:

• ICP101: Bhaskar Acharya, Cadence—"Cadence PHY for PCIe 4.0: Live Correlation Demo Between Silicon Measurement and Sigrity AMI Simulation"
• SYS201: Paul Carzola, Cadence—"Fast-Paced Design IP Development Using Metric-Driven Project Tracking"
• CUS207: Chris Whary, Cadence—"Advanced Node Custom Analog Template Based Layout Methodology"
• CUS104: Louis Francois, Cadence—"Using the Latest Virtuoso Tool Suite to Achieve Extensive Verification of Analog IP in Deep Sub-Micron and FinFET Technologies"

Get more details about CDNLive Silicon Valley and register now!