DesignCon Demonstration of IP for PCIe 4.0 and 16Gbps Multi-Protocol PHY

We enjoyed sharing our latest news with the many people who visited our booth at this year's DesignCon, showing our demonstration of PCIe 4.0 carried on a 16Gbps Multi-Protocol PHY. You can see some of the demo in this ChipEstimate.TV video.

Visitors most valued the performance of the 16Gbps Multi-Link PHY. In addition, attendees were very interested in:

• PCIe 4.0 and 10G-KR support: Yes! Our product does support back-channel link training, the ability to automatically program the TX FIR based on the channel characteristics!
• Long reach and multi-link capability: One of our product’s major customer/partners has already demonstrated in the lab the interoperability of the IP across four lanes at 16Gbps, with their PCIe 4.0 system over a backplane featuring 36dB!
• Continuous DFE adaptation: Yes, our product’s receiver DFE is continuously adaptive. This means that during live traffic, the IP DFE coefficients automatically adapt to compensate for temperature/voltage changes and aging of the connectors and of the backplane.
• The PHY IP exceeds the most stringent requirements of the datacenter and networking markets: 10 years life time, 110C for electro-migration, Vdd +10/-5%.