Elpida announces 30nm, low-voltage, low-power, 2Gbit DDR3 SDRAM with TSV (through silicon via) 3D option

The headline pretty much says it all. Memory vendor Elpida hit all the DRAM high notes in its most recent announcement of a new 30nm DDR3 SDRAM. First, Elpida says in one place in the press release that it will produce this SDRAM with a “30nm-level” process. However, most of the announcement doesn’t qualify “30nm” with “level” so this may well be a true 30nm process technology, which makes this quite advanced for an SDRAM process technology and ahead of other announces SDRAM production process technologies. For system designers, however, what’s important is that the 30nm process will produce SDRAMs that run on 1.35V, consume 15% less operating power and 10% less standby power than the company’s 40nm SDRAMs, and these SDRAMs can meet the DDR3-1866 transfer rate (although not at 1.35V). At 1.35V, the SDRAMs' operation is “limited” to DDF3-1600.

One really notable part of the Elpida announcement is its mention of 3D assembly using TSVs (through silicon vias). The Elpida release says: “The company also plans to use the process together with Through Silicon Via (TSV) technology to support one-chip memory solutions for mobile phones, digital still cameras and PC DRAMs.” Of course, the producers of high-volume mobile and consumer products are already using 3D chip packaging, but mostly rely on wire bonds to connect the stacked chips. A 3D assembly process based on TSVs promises a host of benefits including faster interchip I/O rates, lower operational power, less heat, and even lower assembly costs (at least eventually). So the inclusion of this mention in an SDRAM press release is really more significant than it may seem at first glance. However, system designers only realize these benefits when the chips are designed for TSVs--thus the importance of including this information in this announcement.