Elpida, Powertech Technology, and UMC team up to mate SOCs and memory using 3D design and assembly, targeting 28nm node

The idea of 3D wafer stacking isn’t new. I wrote an article about 3D assembly of silicon die and entire wafers using through-silicon vias (TSVs) more than 20 years ago in an EDN series titled Decade 90, but it was only an experimental technology way back then. Over the past 10 years, SIP or system-in-package assembly techniques have taken the compact mobile product world by storm, particularly in products such as cell phones where reduced component volume translates directly into reduced end-product size and a corresponding increase in the perceived value of the end-product. Existing techniques rely heavily on wire-bond stitching or intermediate carrier boards to implement the 3D assembly. It’s clear that more automated, lower-cost die-stacking and -attachment techniques are in the industry’s immediate future and there’s no better indication of that imminent advance than the recent cooperative 3D-assembly development announcement by DRAM-maker Elpida, Taiwan assembly house Powertech Technology Inc (PTI), and silicon foundry UMC. The three companies plan to work together to develop more automated, less costly methods for designing ICs that incorporate TSVs and for packaging the resulting chips into 3D assemblies. The announcement specifically mentions targeting 28nm as well as other process nodes.

For its part, Elpida developed an 8-bit DRAM based on TSV technology last year. The company claims that the TSV interconnects allow much wider interconnect between the DRAM and the associated SOC, which can increase the bandwidth between the DRAM and the SOC, lower the transfer rate and therefore lower the power consumption (because more bits are transferred per clock), or both. However, to be useful, Elpida’s TSV-based DRAMs need appropriately designed SOCs that will mate with the DRAMs. Developing the technology that supports the design and manufacture of such SOCs is UMC’s responsibility in this partnership.

Bonding these chips together and packaging them is PTI’s responsibility. PTI already claims to have been developing its 3D-assembly expertise since 2007 and has begun working with silicon die as thin as 50um. The company has already worked on SIP assemblies that stack as many as eight die in one package and it is working on the ability to stack 16 die in one low-profile package. These existing 3D assemblies do not use TSV technology. Developing TSV assembly techniques is the next step for PTI, working in conjunction with Elpida and UMC.