How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Consider an autonomous mobile robot moving through a warehouse. Cameras and lidar continuously capture its surroundings, and an AI accelerator processes those inputs for object detection, localization, and path planning. Control modules send commands to motors and actuators, while selected sensor and inference data are written to local storage. All of this happens at once, so both connectivity domains must stay active while the robot operates.

PCIe 5.0 and Ethernet map naturally onto these two domains. PCIe 5.0 provides the local connection to accelerators and storage. Ethernet carries traffic across the larger platform, and this article focuses on 25G Ethernet. The demonstration shown above uses 25GBASE-KR, the 25G Ethernet interface defined for electrical backplane-style channels.

Instead of implementing a dedicated PHY for each protocol, designers can use a multi-protocol PHY: a single high-speed PHY whose lanes can be configured for different interface standards. Multi-protocol PHYs can support additional standards as well, but the PCIe 5.0 and 25G Ethernet pairing offers a clear example of how the approach works. Separate lanes are assigned to each protocol, allowing both to operate concurrently without duplicating the PHY.

PCIe 5.0 and 25G Ethernet operation within a multi-protocol PHY for physical AI connectivity

Assigning Traffic and Lanes

PCIe 5.0 is suited to traffic that stays close to the compute SoC. In the warehouse robot, it can connect the SoC to an NPU, GPU, NIC, or NVMe SSD, carrying sensor data, model data, intermediate results, and inference output between high-performance components.

25G Ethernet serves the rest of the platform. It can link camera and sensor modules, distributed compute, and control subsystems located elsewhere in the robot, so physically separated modules can exchange data without routing everything through the local PCIe fabric.

The two paths are separate but closely linked. Sensor data arrives over 25G Ethernet and moves to the AI accelerator over PCIe 5.0. The resulting inference output then drives a control decision while selected information is written to storage. Because these activities overlap during normal operation, both links must carry traffic at the same time.

A multi-protocol PHY meets this requirement by dividing its lanes between the two protocols. One lane group operates as PCIe 5.0, while another operates as 25G Ethernet. Each lane is configured for a single protocol, so no individual lane carries PCIe and Ethernet traffic simultaneously. Concurrency comes from running both lane groups in parallel within the same PHY.

Simultaneous PCIe 5.0 and 25G Ethernet (25GBASE-KR) operation over separate lanes of a multi-protocol PHY

Reducing PHY Duplication

Without a multi-protocol PHY, the design needs one PHY for PCIe and another for Ethernet. Each brings its own high-speed analog circuitry, clocking resources, lane planning, physical integration work, and verification effort.

Robots, drones, smart cameras, and other autonomous machines operate within practical limits on silicon area, package size, power, thermal capacity, and cost. A second PHY consumes resources that could otherwise go to compute, memory, control functions, or other product features. Consolidating PCIe 5.0 and 25G Ethernet onto one multi-protocol PHY avoids that duplication.

The savings apply at the PHY level. PCIe and Ethernet still require their own digital functions: a PCIe controller, an Ethernet MAC/PCS, and the associated integration logic. The multi-protocol PHY provides the physical lanes for both protocols; it does not combine or replace those digital subsystems.

Adapting the Lane Plan to the Product

The balance between PCIe and Ethernet varies by application. A robot with several local accelerators may need more PCIe bandwidth, while a platform with many cameras, sensor modules, or control units may need more 25G Ethernet links. Autonomous mobile robots, humanoids, drones, and industrial machines often share similar compute and sensing functions, yet the number and placement of their accelerators, sensors, storage devices, and control modules can differ considerably.

A configurable multi-protocol PHY lets the lane allocation follow those requirements. Designers can start from a common PHY architecture and assign lanes to PCIe 5.0 or 25G Ethernet for each product. Across a product family, one variant can dedicate more lanes to accelerator traffic while another reserves more for platform connectivity, without redesigning the PHY each time, provided it supports the required configuration.

Planning the Configuration Early

Concurrent operation must be planned from the start of the design. It should not be assumed simply because a PHY supports both protocol standards.

The intended configuration must account for the number of lanes assigned to each protocol, PCIe link width, Ethernet port configuration, PLL resources, reference clocks, firmware support, and compliance requirements. Clocking deserves particular attention because PCIe and Ethernet may use different reference clock assumptions. Some mixed-protocol arrangements may also raise compliance considerations when PCIe links operate at lower generations, so the full set of operating modes should be reviewed, not only the maximum data rates.

Defining the protocol mix, lane allocation, and clocking strategy early gives the design team time to select the right PHY configuration and verify that every intended operating mode is supported.

Conclusion

Physical AI systems need both high-bandwidth local links and reliable connectivity across the platform. A multi-protocol PHY addresses both domains with a single PHY, running PCIe 5.0 and 25G Ethernet concurrently on separate lanes. The result is less PHY duplication, more efficient use of silicon area and integration resources, and the flexibility to rebalance lanes as product requirements change.

To learn more about Cadence's multi-protocol PHY solutions for Physical AI, visit cadence.com or watch the video, "Cadence Multi-Protocol PHY Demo: Simultaneous PCIe 5.0 and 25G Ethernet Over a Unified Interface".