Interconnect Validator and its Significance

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP components that link together multiple processor cores, caches, memories, and dozens of other IP blocks. These interconnects are enabling new generations of low-power servers and high-performance mobile devices. However, sophisticated interconnects have to be highly configurable, which creates unique challenges for SoC integrators and verification engineers. Seemingly minor variations in the configuration of these interconnects can introduce unintended bottlenecks that degrade SoC performance.  To aid SoC developers, Cadence provides an integrated solution for interconnect verification and performance analysis. The solution includes the Cadence Interconnect Validator (discussed in this post) and Cadence Interconnect Workbench (discussed in the future posts).

Interconnect Validator is a system VIP component that works in conjunction with interface VIP components. It verifies the data integrity as it passes through the interconnect. Interconnect Validator monitors all ports on an SoC’s interconnect, deploying clever algorithms to track data items as they are transformed and transported through the interconnect to their destinations, and checking proper routing of responses. Accounting for the data transformations associated with crossing interface protocol domains, Interconnect Validator automatically handles upsizing, downsizing, and splitting.  

Interconnect Validator supports the verification of both non-coherent interconnects and coherent interconnects such as those based on the ARM® AMBA® 4 AXI™ Coherency Extensions (ACE™) and AMBA 5 CHI (Coherent Hub Interface) specifications.

The following block diagram shows how interface VIPs and Interconnect Validator are used in an interconnect-centric environment.

In non-coherent mode, Interconnect Validator provides the following verification capabilities:

• Mixes and matches any supported protocols (e.g., APB, AHB, and AXI)
• Supports any number of masters and slaves
• Accommodates independent address forwarding for each master
• Handles data splitting, upsizing, and downsizing
• Supports INCR, WRAP, and FIXED addressing modes
• Supports internal address ranges and unmapped access
• Supports transaction ordering
• Handles slave power-down, interconnect reset, and dynamic address forwarding

 In coherent mode, Interconnect Validator provides the following additional verification capabilities: 

• Supports any number of outer and inner domains
• Verifies snoop conversions, snoop propagation, and snoop filter operation
• Checks cross-cache line operations
• Supports DVM transactions
• Verifies barrier transactions
• Supports interconnect-initiated operations
• Supports L3 cache operation

Behavior of Interconnect Validator is easily customizable. Design-specific checking and user-created rules can be added and standard protocol rules can be bypassed or modified. Besides providing out-of-the-box support for standard ARM AMBA and OCP protocols, Interconnect Validator could be used in the systems which utilize non-standard, custom-developed protocols.

Interconnect Validator assists verification effort by providing a coverage model of all transactions exchanged between masters and slaves within an SoC. The coverage model addresses both coherent and non-coherent aspects of interconnects operation.

Interconnect Validator supports both SystemVerilog and e verification languages and associated methodologies including UVM, OVM, VMM, and eRM.

Dimitry Pavlovsky