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Coming back from the PCI-SIG Developer Conference Asia-Pacific Tour 2015 in Japan, and the PCI Compliance Workshop in Taipei, it was encouraging to see the engineers’ high level of interest in PCIe 4.0.
The engineers attending the conference and workshop in general were all in good moods, I wondered if it was reflective of the quality of the food that was being served to those in attendance. In Tokyo, the PCI-SIG committee that arranged the food deserved kudos. The sashimi was fresh, the food presentation was worthy of a Michelin-starred restaurant, the desserts were sublime, and, amazingly enough, there was an ample supply of food. The food in Taipei was also amazing and, even for the PCI Compliance workshop attendees, there was an amazing array of food, including an overflow of freshly cooked, shelled sweet shrimp, arrays of both western and Chinese food. It is difficult to decide which I liked best: Tokyo or Taipei. But if all the conferences in the US had the same quality of food, I would have to justify attending more conferences!
Culinary treats at PCIe conferences in Asia.
In Tokyo, Cadence showcased our latest generation 28nm PCIe PHY, which passed the PCIe 3.0 compliance test at the San Jose PCI Compliance Workshop in June 2015. We also demonstrated the Cadence Verification IP (a.k.a. VIP) version of the PCIe solution. Some may not be aware of Cadence’s VIP portfolio (a future blog post will focus on VIP in greater details), but it is an indispensable tool that any engineer should consider using in order to perform a full-chip verification, validating that the entire subsystem IP is integrated and operating correctly. Many customers did not realize that Cadence is not only the paramount EDA tool supplier in the industry, but offers a complete end-to-end IP suite, from VIP to PHY IP and Controller IP for the PCIe protocol.
Cadence VIP for PCIe demos
Increasingly, more engineers have shown interest in or were developing systems or ASICs utilizing PCIe 4.0, and were a little disappointed that PCIe 4.0 is not yet at draft 0.9 and is instead in draft 0.5. Cadence is ready for PCIe 4.0, and has been tracking and implementing the changes in our PCIe solution. But PCIe 4.0 at draft 0.5 has not deterred early adopters. There was consensus amongst Cadence and other exhibitors at the Developer Conference that were already supporting customers developing PCIe 4.0 ASICs. This highlights the main benefit of PCIe 4.0—which doubles the throughput from 8GTps to 16GTps—and how this is driving semiconductor and system companies to adopt PCIe 4.0 ahead of ratification. The demands for bandwidth in datacenter, mobile, and cloud applications means that the industry is looking for ways to eliminate the 8GTps bottleneck. For more details about the PCIe 4.0 update, please watch this video.
PCIe STANDARDS PERFORMANCE COMPARISON
Table courtesy of PCI-SIG
Taipei hosted both a Developer Conference and a PCI-SIG Compliance workshop. Cadence sponsored one day of the compliance workshop, where we saw many companies working to achieve PCIe 3.0 compliance. Many engineers came by inquiring about when PCI Express compliance testing for PCIe 4.0 will be available. With PCIe 4.0 still in draft 0.5, it is too early for PCIe 4.0 compliance testing to be released. But, when released, it will consist of the same five different test areas currently used on PCIe 2.0 and 3.0. The five areas are electrical, configuration, link protocol, transaction protocol, and platform BIOS testing.
PCIe 4.0 may be only be in draft 0.5 and no compliance testing kit is ready. But the interest is there and ASIC/semiconductor or system manufacturers and early adopters are beginning work on their PCIe 4.0 solutions. The ecosystem of suppliers is also ready to enable the early adopters, The next 12 to 18 months until the new specification is fully ratified in 1H’17 will be an interesting time for PCIe 4.0: will the need for faster throughput force some of the companies out there to forge ahead of the PCI-SIG, or will this need create an alternative?
How about you? Do you see the need for PCIe 4.0 in your application?