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Community Blogs SoC and IP > Less is More With MIPI I3C
Jacek Duda
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Less is More With MIPI I3C

22 Aug 2016 • 1 minute read

There is little doubt that Internet of Things has become the next big thing in business, in particular in semiconductor IP. The growing number of devices monitoring and adjusting our surroundings – lighting, temperature, sound volume and others has exploded in the recent years, and actually, so did the number of pins within an SoC that is needed to connect them all.

Also, the use cases for the new generation of sensors make extensive use of the always-on feature – many of the new devices are wearables, or exist within mobile devices like smartphones or tablets. Therefore, the need for power efficiency is higher than ever. 

Last but not least, until now there has not been a standard for connecting sensors – both I2C and SPI co-existed, each with its pros and cons, but neither could meet the requirements of a modern sensor application, where the peripheral device would have the ability to notify the application processor when it has data to transfer, at least not without costly extra wires.

For this reason, MIPI Alliance has introduced the concept of the I3C specification. At the core, I3C aims to standardize on the sensor interface, and introduce a variety of improvements over I2C and SPI, while preserving compatibility with widely adopted I2C.

The improvements include reduced pin count (only 2 wires), higher throughput (up to 40Mbps), and lower implementation cost. There are also new features available in the standard that are not present in I2C or SPI, like multi-master support, dynamic addressing and common command codes. Moreover, I3C puts a lot of focus on advanced power management, which translates to less energy consumption per amount of data sent and longer battery life.

Cadence has been engaged in the development of the I3C specification since early stages, and is now shipping IP implementations to early adopters (the final release of the specification is still pending in the moment of writing). Thanks to continuous tracking of specification changes and flexibility of the architecture, we’re able to supply customers with feature sets that take full advantage of the new standard, while keeping power and area numbers at the minimum.

To find out more about Cadence offering for I3C IP, please visit our website here.


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