New White Paper discusses the challenges of chip design based on AMBA 4

ARM’s series of AMBA specifications have become a de facto standard for SoC (system-on-chip) interconnects. ARM introduced the first version of the specification more than 15 years ago and has now released the latest version of the specification, called AMBA 4. The AMBA 4 specification is actually a collection of specifications (including AXI4, AXI4-Lite, and AXI4-Streaming) that may well revolutionize the future of high-performance SoC interconnects. The new AMBA 4 protocols extend the AMBA 3 protocol to improve interconnect performance and quality of service. The AXI4-Lite specification is a simplified implementation of the specification that’s designed to meet the needs of FPGA-based designs through simple control-register interfaces and reduced wiring congestion. AMBA 4 also supports non-address-based, point-to-point communication through the new AXI4-Stream protocol. AMBA 4 resulted from a collaborative effort by more than 35 of the industry’s leading OEM, semiconductor, EDA, and IP vendors. The AMBA 4 specification is available now as a PDF download to ARM licensees on ARM’s Web site. The new specification directly addresses the needs of high-performance, low-latency, and low-power chip designs.

The AMBA 4 protocol is a natural extension of the AMBA 3 protocol and it introduces many new features such as 256-beat burst support for improved performance, Quality of Service (QoS) signaling for multi-master support, the AXI4-Stream protocol for non-address-based, point-to-point communication among masters and slaves (especially useful for data streams commonly used for moving video and audio on an SoC), multiple region interfaces, and so on. Additionally, the AMBA 4 specification cleans up many issues with the earlier AXI3 specification such as write-response dependencies and clarifies the meaning of certain pins. These new features add yet another level of complexity to AMBA-based SoCs. Some of these features specifically target SoCs with multiple cores, giving rise to many new challenges for both IP designers and SoC integrators.

As complexity grows, verification becomes ever more difficult. An industry survey shows that as many as two thirds of all SoC designs need respins and some SoCs are re-spun as many as four times. Because the costs of finding and fixing bugs in the pre-silicon stage is so much lower than the costs of finding them during the later stages of the design, thorough design verification has become a truly essential part of the design process. Bill Watt, Denali’s Principal Software Engineer, and Sanjiv Kumar, Director of Verification IP Products at Denali, have jointly written a White Paper that deals with many of the design and verification challenges SoC, ASIC, and ASSP design teams may encounter during design. The White Paper is available now for download. Click here.