Specialty semiconductor foundry TowerJazz licenses “Y-Flash” IP to “leading” digital foundry

TowerJazz, the specialty semiconductor foundry created by the merger of Tower Semiconductor and Jazz Semiconductor in 2008, has announced that it has licensed its “Y-Flash” MTP (multiple-times programmable) CMOS memory IP to an unnamed, “leading” digital foundry. TowerJazz’s Y-Flash IP creates a Flash memory cell with standard CMOS processing. In other words, the Y-Flash memory cell has only one gate and it’s a floating gate so there’s no cost adder required to place a Y-Flash memory array on a standard CMOS ASSP, ASIC, or SOC. Conventional Flash memory cells have a floating gate buried beneath a conventional FET gate and fabrication of Flash memory cells may require the use of ten or more additional masks to create that extra gate and the insulation oxides needed to isolate the floating gate from the rest of the FET. TowerJazz’s Y-Flash cell design requires no additional mask steps, or can be performance-enhanced with two additional but "non-critical" mask steps. TowerJazz’s press release says that Y-Flash IP is well suited for memory arrays as small as one bit and as large as 256 kbits, although a technical paper on the TowerJazz site sets the practical upper limit for Y-Flash memory-array capacity at 1 Mbit.

The Y-Flash memory cell employs an asymmetrical FET design with a small N+ source and a large N+ drain. The gate oxide and the floating gate completely cover the source and drain areas in addition to the channel, unlike modern FET design where the gate and gate oxide overlap the source and drain slightly or not at all. Applying a positive programming voltage to the Y-Flash cell’s drain region and connecting the source region to ground drives electrons into the floating gate through channel hot electron (CHE) injection from the drain region, thus programming the cell. Connecting the drain diffusion to ground and applying a positive voltage to the source drives holes into the floating gate through band-to-band tunneling (BBT), which erases the Y-Flash memory cell. A consequence of this program/erase mechanism is that the Y-Flash memory cell’s gate need not be connected electrically to any portion of the memory (or anything else for that matter) and no bit-cell-select transistor is needed.

All programming and erasure is performed by appropriate row and column selection transistors fabricated with LDMOS FETs. As a result, TowerJazz claims that Y-Flash memory cells can be 5x smaller than conventional Flash memory cells. Even so, TowerJazz research indicates that the Y-Flash cell can be reliably programmed and erased several hundred thousand times, making Y-Flash cells attractive as non-volatile storage cells for frequently changed data such as calibration constants and user settings or when there’s not much code to store on chip.

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