ST Microelectronics’ SPEAr1300 embedded MCU features 600MHz dual-core ARM Cortex-A9, DDR2/DDR3 SDRAM controller

A few days ago, this blog discussed the “big resistor” model of SDRAM power consumption (see Marc Greenberg’s “big resistor” model of semiconductor DRAM power consumption) and that blog entry ended with this statement:

“It might also be a very good idea to design your system so that it can accommodate more than one DDR variant. That way, time and circumstance can determine which DRAM technology gets used at any given time. That idea, coincidentally, is the topic of a Denali White Paper scheduled to be released in the near future.”


Well, designing advanced SOCs so that they can mate with multiple generations of SDRAMs is not just a nice recommendation based on a convenient theory--it happens in the real world. Case in point: ST Microelectronics’ announcement of the company’s new SPEAr (Structured Processor Enhanced Architecture) 1300 family of embedded microprocessors that target high-performance connectivity and embedded applications.

ST Micro’s new embedded microprocessor family typifies the current evolutionary step in high-end embedded processing platforms. The SPEAr1300 embedded processor family is based on a 600-MHz, dual-core implementation of ARM’s Cortex-A9 32-bit microprocessor. Each of the two Cortex-A9 processor cores has separate 32-kbyte L1 SRAM instruction and data caches and the chip adds a unified 512-kbyte L2 SRAM cache and a 32-kbyte boot RAM so the embedded processors in this family can easily handle the processing requirements of many high-end embedded applications. The SPEAr1300 embedded microprocessor family includes a host of different peripheral interfaces commonly used in today’s high-end embedded applications--USB, PCIe, and SATA, for example--and also includes many internal peripherals needed to create complete systems as shown in the block diagram below:




Like most of the embedded microprocessors being designed today, ST Microelectronics’ SPEAr1300 family does not include a lot of on-chip memory beyond the L1 and L2 caches for the dual-core ARM Cortex-A9. Yet that 600-MHz dual core processor will have quite a thirst for instructions and data so a large memory must be somewhere nearby. Like most SOCs designed today, the SPEAr1300 processor family is designed to mate to the current leader in low-cost memory storage: DDR SDRAMs. To do this, the SPEAr1300 devices include a DDR SDRAM controller capable of driving either DDR2 or DDR3 SDRAM. This conservative design approach--accommodating two generations of SDRAM--grants system designers maximum leeway and flexibility in developing systems along a wide price/performance continuum and will help to drive the chips’ sales volumes by making sure that the embedded processors suit the widest possible range of applications.

As previously mentioned, Denali will soon release a White Paper discussing the topic of multigenerational DDR SDRAM support in more detail.