ST Microelectronics’ SPEAr1300 Embedded Processor family employs Denali Databahn DDR controller and PHY to control multiple DDR SDRAM generations

Last month, this blog described the new SPEAr1300 Embedded Processor family from ST Microelectronics and focused on that chip family’s ability to control either DDR2 or DDR3 memory. Designing the ability to control multiple DDR SDRAM generations into an SOC like the SPEAr1300 is a good idea because it gives the system designers using the SOC maximum flexibility in selecting a memory technology that best fits the end product’s cost and performance goals. Today, ST Microelectronics and Denali announced that the SPEAr1300 family employs Denali’s Databahn SDRAM controller IP and synthesizable PHY to achieve this memory flexibility. The press release also discloses that ST Microelectronics’ SPEAr600 family of Embedded Processors, which can control DDR1-400 and DDR2-666 SDRAMs, also employs Denali’s memory controller and PHY IP.