Tech Shanghai Drives Innovation by Overcoming Challenges

Far more often than we imagine, we think about China within the context of the complicated technology we create. The ‘I want it now’ generation is driving the need for higher performance products and that need is increasingly fulfilled by companies in China. That’s why we went for Tech Shanghai 2016. And we brought gifts.

The electronics industry in China can be measured as a million souls, although the number is probably even higher. With over two decades of success and annual awards the country has emerged as a serious player. More than that – show organizers indicate that there is a possibility of China-based IC growth at 15%, while the global rate growth is only 3.8%. And they plan 60 seminar sessions with 2000 attending engineers, showing the potential and reality of electronics in the region.

With topics like industrial and medical electronics, smart and wearable devices, IoT and home smart solutions, this years’ Tech Shanghai was the place to be. Cadence presented three keynotes, highlighting SoC design challenges for DDR, high-speed SerDes and 3D Electromagnetic Simulation. The common themes these presentations where the deep Cadence high speed design expertise, advanced node knowledge, and orientation to delivering quality to our customers.

Figure 1: Explosive growth in datacenter traffic and scope of datasets for analysis

DDR 4 is the latest standard that offers high capacity memory bandwidth with speed and electrical efficiency.  The goal however is to meet the requirements of always-hungry processors which demand higher performance memory subsystem.  Achieving the high data rates required of these memory subsystems significantly increases system level challenges. This requires a DDR interface IP that can deliver high throughput, such as the current industry best 3200 Mbps. Process nodes as low as 14/16nm, and smaller, provide the crucial performance and low power advantages to achieve memory interface IP with high throughput. Furthermore, designing a memory subsystem to meet the performance demand involves much more than an IP designed to operate at 3200 Mbps. More emphasis must be placed on architecting an interface through the entire SOC, package and board that can reliably transfer data at these high data rates.

Figure 2: Ever growing demand for high speed SerDes interface IP

The second keynote addressed another big trend in high speed SerDes interfaces and their application to serve insatiable demand for throughput in cloud servers and datacenter networking. The speed demand will simply not slow down! Our latest 16 Gbps SerDes supporting PCIe 4 was on display at the event, a key standard interface that is impacting datacenter architecture. It can be used to increase the bandwidth and data transmission rate from server to server, switch to switch, and server to storage, enabling even larger dataset analysis and other complex cloud services.

And the final keynote from Cadence highlighted 3D electromagnetic simulation to address the chip, package and board signal integrity co-design challenges. Cadence has achieved seamless transition from layout to 3DE, performing 3DEM with other 2D/3D simulation, links-to-circuit, point of control tradeoffs for high-level analysis involving 3DEM and accessing various types of 3DEM analysis (e.g. static vs. full-wave).

It seems like Tech Shanghai is the most popular destination event in China. A beautiful location, and clearly a hub of innovation and creativity.