The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

20 Jun 2016 • 1 minute read

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets all over the world. We see a lot of market forces at work, creating urgency for PCIe Gen4 dynamics. Designers, system architects, engineers and engineering managers will be the driving force behind another PCI-SIG event. Taking place on June 28-29 2016 at the Santa Clara Convention Center, California, this prestigious event is filled with value and learning opportunities.

Figure 1: Server rack in today's cloud computing infrastructure

This year’s presentations and demos from Cadence are especially compelling:

PCIe Gen4 controller and PHY IP
PCIe Gen4 interoperability demonstration with Mellanox
PCIe Gen3 controller and PHY IP
PCIe interface verification with Verification IP (VIP)

Plus, our technical expert Gopi Krishnamurthy will be co-presenting with ARM, Tuesday @ 1pm.

“Implementing PCIe ATS in ARM-based SoCs”

“Cadence has been a member of the PCI SIG for many years. We actively participate in the developers’ conferences, showcasing our advanced technologies and demonstrating thought leadership through paper presentations. We are at a key stage in the evolution of the PCI protocol with v4.0 coming close to ratification and Cadence will demonstrate a number of IP solutions that address this new generation of the protocol standard.

A large number of Cadence engineers, architects, and product line owners will participate in the DevCon in June, providing an opportunity for discussion and collaboration with the large PCI community”, Arif Khan, Product Marketing Director.

The complete agenda of the convention can be found here. For more information on registration and accommodation rules please go to the event’s official website