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At this year’s Technology Symposium, TSMC disclosed that they will provide two N7 processes, one for high-performance computing and one for mobile, presumably optimized for performance versus power and area. The other important announcement was the new 16 FFC automotive process for ADAS. Stay tuned as Cadence makes plans for these technologies!
Our news was focused on 16FF+. At the Symposium we demonstrated multi-lane interoperability of our 16Gbps multi-link and multi-protocol PHY PCIe 4.0 IP with Mellanox PCIe 4.0 PHY IP. This interoperability significantly reduces adoption risk for the industry’s soon-to-be PCIe 4.0 specification. Read more details here. This solution was configured with four lanes running concurrent traffic. Although a typical configuration for next-generation servers, storage and networking, the testing was comprised of a series of demanding tests. The testing demonstrated the IP exceeds PCIe 4.0 architecture requirements in terms of insertion loss, at the same time demonstrating a bit-error rate (BER) below 10-15.
Also announced was the silicon demonstration of our DDR4 and LPDDR4 IP in 16FF+ operating at 3200Mbps. Read more about those details here.
All around, the TSMC Technology Symposium wrapped up another big year of technology innovation!
Waouu: Cadence PCIe 4.0 PHY Interoperability with Mellanox PCIe 4.0 System !