Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)

This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser.  In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.

Highlights:

• The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification
• The demo shows Cadence's PCIe Gen3 high performance x8 configuration operating at full speed 500Mhz clock rate with a transfer rate close to 8GT/s
• The display trace shows the PCIe Gen3 IP transition from Gen1 speed 2.5 GT/s to Gen3 8GT/s
• LTSSM flow graph showing equilibrium between upstream and downstream packet transfers and speed of operation at 8GT/s

Please come back soon to view Part 2 of 2 showing the advanced features of Cadence's PCI Express Gen3 IP.

Stella Murphy