Tensilica, Design, and Verification IP Blogs

While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this had on me in my previous post, A Walk Through DesignCon Turns Into a Long Journey). There was so much hardware, in fact, that I felt like I was walking through a giant Fry’s store. The impression was so strong that my first thought was “Why is Cadence at this show?” I would soon have my answer.

If you’ve followed Cadence for any length of time, you’re sure to have heard about System Design Enablement. SDE is the name we put on our vision for extending out from the core capabilities of electronic design automation to tie in IP, software, and deep integration to the other aspects of system design that extend beyond the chip. Having said that, for many in the industry, SDE is still a fluid term that means different things to different people. It was about to become much clearer for me.

I focus on IP, so was particularly interested to see the reaction to a paper presented by one of our R&D directors and titled “DDR-4400 IP Model Development Using AMI Builder”. The presentation spawned several conversations which carried over into our booth on the exhibit floor. While the typical attendee at this show was not seeking IP solutions per se, they were definitely seeking solutions to help them with IP integration into an SoC, SoC integration into packages, package integration into boards, and board integration into systems. So, in that context, the IP presentation was very valuable, as demonstrated by the interest it generated.

And that’s when the lightbulb switched on for me. This was SDE in action. Since I naturally tend to focus on components (the IP block, the SoC, the package, etc.), I was missing the glue that ties all the components together to make a system. Obviously signal integrity analysis is needed at the package and board level, but it requires fast generation of high quality models at the IP-level to work. The models, and especially the model generation mechanism, are the glue. So here was a real-world implementation of SDE that tied IP-level functionality to system-level performance.

Whether they call it SDE or something else, every company in the EDA ecosystem must contribute to the glue that makes systems come together. Cadence has a unique place in the ecosystem since it is the only company that plays a leading role in IP development, SoC design, package design, and board design. And while the Cadence vision is broader than just these 4 elements, these elements are certainly the essential pillars needed to deliver meaningful system design enablement.

Cadence delivered several presentations at the event. You will soon be able to download them from our DesignCon event page.