Tensilica and Design IP Blogs

PCI-SIG Developer’s Conference 2017 was held in Santa Clara, California in June this year where several hundred customers from more than a hundred unique companies visited the conference. The next-generation PCI Express (PCIe) 5.0 specification was announced with plans for ratification in 2019. The announcement had a supporting quote by Cadence confirming our long-term commitment to developing products for PCIe interface protocols. The schedule for adoption of the new standard has been accelerated to less than 2 years to keep up with the networking and storage throughput requirements of the data center. The PCIe 4.0 specification v0.9 was also released and is expected to be ratified later this year.

The Cadence PCIe 4.0 integrated PHY and Controller IP solution had a good showing at a demo of x16 16Gbps PCIe PHY based on 16nm running at speeds over 22Gbps and the complete PCIe 4.0 solution (PHY+Controller) interoperating with a Mellanox end-point.

Other news highlights

• • • • • • • • • Cadence 16Gbps Multi-Lane Multi-Protocol PHY solutions based on TSMC 16nm achieved PCIe 3.1 Compliance in the very first attempt
                • Cadence PCIe 4.0 solution successfully inter-operated with all other solutions and passed all FYI tests, including lane margining
                • Cadence PCIe 3.0 PHY on TSMC 28HPC+ and PCIe 2.0 PHY on TSMC 28HPC were also recently added to the integrator’s list

With all these developments, it’s no surprise that Cadence PCIe IP is now the best-in-class IP available on the market today. If you’re interested in using Cadence IP for your PCIe solutions, want to set up a demo, or want to know more about the IP, please contact Sachin Dhingra at sdhingra (at) cadence (dot) com or visit the PCIe Product Page for more details.