What’s on the Horizon for NAND and DRAM?

Young Choi, Guest Blog for Denali Software

January is a time where lots of planning and forecast are made, with high hopes usually. Semiconductor memory industry, after several years of prolonged downturn, finally started to see some glimpses of recovery lately. Prices are improving, product migrations happening, new process node migration providing production efficiency and hopefully more profitability to the manufacturers.

The information and data that UBM TechInsights has been collecting on commodity DRAM and NAND Flash products clearly show how semiconductor memory industry has been improving their efficiency measured in terms of Mbit per mm2.

For commodity DRAMs, the latest 40 nm class DRAM products show their efficiency of 34Mbit per mm2. When compared to the previous 50 nm class DRAM, 40 nm class shows over 40% improvement. When cost per bit matters the most, 40 nm class DRAM will clearly provide the much needed cost advantage to those manufacturers who have this technology. For those who don’t, they need to find a better way of securing their profitability. When innovation and investment are the name of the game, the gap between the haves and have-nots are obvious, and hence, there is constant movement of joint ventures and merger and acquisitions to create economies of scale. Recent movement of Micron and Elpida, with their respective partner companies in Taiwan, is a clear sign of this. Perhaps later in 2010, we might be able to see the first 4F2 cell based commodity DRAM products. While some DRAM manufactures still have products with 8F2 cell, new 4F2 cell designs combined with smaller geometry would deepen the gap between DRAM makers.

For NAND industry, the trends have been staggering. Introduction of 30 nm class products certainly has contributed to the higher efficiency of commodity NAND Flash products for sure. For NAND, luckily three-bit per cell (X3, TLC or 3-bit MLC) and four-bit per cell (X4, or 4-bit MLC) also helped push the envelope further beyond the lithographical limit in terms of bit density (Mbit per mm2). While all of the major NAND manufacturers (Samsung, Toshiba/SanDisk, Intel/Micron and Hynix) have announced their three-bit per cell and/or four-bit per cell NAND products, there are still some concerns about their reliability and performance. This is reminiscent of the times when MLC (two bit per cell) based NAND products were first introduced. The industry and the market had managed the reliability and performance issues successfully and MLC had become the mainstream NAND technology in many data applications. One can expect that the same would happen to three- and four-bit per cell NAND technology, eventually.

While the past history or performance of the two key commodity memory technologies, DRAM and NAND, has been impressive and even remarkable, the future has a lot of uncertainties. To help us understand what to expect in the future, the presentation which was given by Kinam Kim at Samsung can be a good reference. This was also published on the Semiconductor International website. A patterning limit chart is shown below:

Of course, patterning limit is not the only obstacle to achieve more efficient DRAM and NAND products. There are many other technical challenges for DRAM cell, storage capacitance, isolation, leakage, reliability, floating gate vs. charge trapped flash, double patterning, immersion lithography, so on and so forth. What about new technologies to make DRAM storage cell a thing of past? What about 3D memory?

It appears as though the semiconductor memory industry is following the curves shown above (fairly closely so far). The 40 nm class DRAM products and 30 nm class NAND Flash products that were announced in 2009 are the proof. The real test within the industry will come in 2010. Will we see 30 nm class DRAM in 2010? How about 20 nm class NAND Flash? It remains to be seen but some early signs seem pretty promising. It’s January, a month of high hopes and expectation and a lot of planning for another year. Let’s hope for the best of the semiconductor memory industry in 2010.

PS: 2010 is a New Year for us as a company, too. Semiconductor Insights, which has been a leader in providing technical intelligence and intellectual property professional services to the semiconductor industry is now called “UBM TechInsights”.

For various DRAM and NAND Flash analysis reports (process analysis, circuit analysis and waveform analysis/functional testing) on the latest 40 nm class 1Gbit DDR3 SDRAM, 30 nm class 32Gbit MLC NAND Flash, 30 nm class 32Gbit Three-bit per cell NAND Flash, 40 nm class 32Gbit Three bit per cell NAND Flash, please visit UBM TechInsights’s Open Market Reports page.