System Verification of Arm Neoverse V2-Based SoCs

The world around us has become data-centric; everything needs data, from navigation maps in vehicles to medical chatbots to autonomous cars. We are using data to solve complex problems and decision-making. The beauty is more data leads to better performance and the ability to extract knowledge from it.

Figure 1: Data Analytics Performance vs Data Volume by Computational Approach

These continuous technology upgrades are leading to an exponential increase in data traffic. It is tough to handle such an enormous amount of data and deliver it with precision, accuracy, and the least latency. The designs are getting bigger and more complex to serve the fast-emerging verticals like data centers, automotive, hyperscale, AI, mobile, and many more.

We need an efficient digital infrastructure ecosystem with advanced chips and infrastructure CPUs with new architecture and tight coupling of CPU and GPU to handle this data tsunami while meeting customer expectations. Arm has announced Neoverse V2 —also called Demeter—a dedicated high-performance core for servers with the highest single-threaded integer performance to meet these requirements.

To avoid data loss and integrity issues, verifying the performance of such SoCs at the system level is highly recommended. It ensures there are no issues like bandwidth throttling or cache-coherency, etc. But, with the growing complexity of new process node technologies, verifying the performance at the system level is increasingly challenging. Cadence System VIP helps to accelerate the system-level performance verification of modern SoCs designed around the Arm Neoverse V2 architecture. It helps to improve productivity and reduce time-to-market (TTM). The Cadence System VIP enables up to 10X efficiency gains in system-level bench assembly, execution, and analysis of SoCs.

Discover how Cadence's System VIP tool suite works seamlessly with Cadence's simulation, emulation, and prototyping engines to automate chip-level verification and improve efficiency by ten times over existing manual processes.

Chip/System-Level Verification Challenges

Chip-level testbench creation, multi-IP, CPU traffic generation, performance bottleneck identification, and data and cache-coherency verification all lack automation. The effort required to complete these tasks is error-prone and time-consuming. 

High performance, power efficiency, and reduced carbon footprint requirements for server processors have led to increased functionality over SoC, 3D-IC packaging techniques, and chiplets usage to keep different flavors of processing cores together. All these reduce controllability and observability and may bring performance and complexity challenges.

System-wide protocols connect multiple IP in collaboration to deliver the expected performance. Ensuring the system's performance requires the validation of these IP and interconnects. For instance, coherency involves cores, interconnects, caches, and memory controllers. Integrating more functionality and multicores suits the customer's expectations and market demands, but it introduces tremendous challenges for the SoC verification teams, such as

• System-level scenario creation for
  • System-wide protocols such as coherency, memory management, virtualization, etc.
  • Performance validation
  • Power estimation
  • Security Verification
  • Complex I/Os include PCIe, NVME, USB4, CXL, etc.
• Domain-specific performance analysis to ensure the expectations are met
• Verification to ensure efficient third-party IP integration
• SoC-level data integrity/cache coherence check before tapeout
• Traditional schemes for chip-level verification are error-prone, time-consuming, and lack automation
• Testbench automation for large-scale subsystems—with the scaling and increasing chip size, automation is mandatory

Missed performance bottlenecks can expose architectural oversights late in the project and can bring all corner cases as cache coherency across SoC can take months. So, we need novel ways to build solutions with improved productivity to capture silicon failures. System-level performance verification is required to ensure the SoC is designed per the architecture intent and to predict its performance.

Cadence System VIP and Full SoC Verification

Cadence provides System VIP, as shown in the figure below, to automate and speed up the SoC-level verification with pre-defined content and tools to meet such demands and the challenges mentioned above.

System VIP, as the name suggests, is verification at the system level above the VIP approaches. The Cadence System VIP Solution addresses the challenges mentioned above and leverages already established engines such as Xcelium, Palladium, and Protium.

• It is a suite of tools and libraries that provide meaningful content for SoC integrators.
• It helps to deliver testbench automation, portable stimulus content, SoC performance analysis, and a system-level data integrity checker.
• It comprises four new products, each working with Cadence Simulation, emulation, and prototyping engines to automate chip-level verification and improve efficiency by ten times over existing manual processes.

Figure 2: Cadence System VIP Solution

1. System Test Bench Generator – Generates ready-to-use chip-level testbenches
2. System Traffic Library – Jump-starts the process to create the chip-level stimulus to stress test performance and catch the corner-case coherency bugs
3. System Performance Analyzer – Offers comprehensive performance analysis for memory subsystems, bus interconnects, and peripherals
4. System Verification Scoreboard – Provides chip-level data and cache-coherency checks

Figure3: Cadence System VIP Views

These are preloaded with ready-to-use content for Armv9 and x86 architectures. Cadence System VIP enables the rapid bring-up and development of sophisticated and reusable content to bring predictability back into SoC schedules. System VIP's System Traffic Libraries speed the development of performance scenarios and domain-specific performance analysis tools, including the System Testbench Generator, System Performance Analyzer, and System Verification Scoreboard, dramatically accelerating the performance analysis process and debugging to root-cause performance bottlenecks.

Summary

Using Cadence System VIP, customers are creating hyperscale, automotive, mobile, and consumer SoCs that can automate chip-level verification and improve efficiency by more than ten times over the existing manual processes.

Learn More

• Cadence System VIP
• Cadence's Arm-Based Solutions
• Cadence Collaborates with Arm to Optimize the Neoverse Implementation
• Improve Verification Efficiency by Up to 10X