Enabling and Empowering OEMs to Design Chips

Introduction

Today, many original equipment manufacturers (OEMs), especially new-generation OEMs, are not shying away from taking ownership of their system-on-chip (SoC) designs and thereby sharing the IP rights with the chip makers. Traditional OEMs are forced to embrace verticalization amid economic, technological, and other challenges, and are moving to design custom SoCs versus buying off-the-shelf SoCs to keep pace with their customers and to expand their market share. Increased competitive pressure to deliver unique products and achieve product differentiation is a major reason for this move. Time-to-market demands that are shortening their design cycles are adding to their woes. The desire for better control over the product design and a greater competitive edge is a motivating factor for many OEMs to take this step.

However, this major shift in the business model introduces many challenges as well. It is imperative for these OEMs to have the latest technology features to outrun the competition. They must work with experienced vendors to be more efficient and to focus their internal effort on differentiation, while leveraging their multi-function cores to do more, faster. For example, a company using Cadence® IP is provided with an automated approach to customization, delivery, and verification of SoC IP. As a result, they can spend more time on the differentiation of their design, while completing their project with the assurance of meeting their performance, power, and area (PPA) requirements.

Cadence tools also can help SoC designers evade their greatest risk—chip failure in the lab. Without simulating the entire signal path, such a failure can’t be detected earlier. With today’s electromagnetic (EM) tools, designers must take shortcuts in interconnect modeling, such as relying on the quasi-static solver or hybrid solver or not optimizing the interface. Whereas, Cadence ensures all the pieces are set up, the design portions including the IP are delivered, and all the modeling is performed accurately using full-wave 3D field solvers. Cadence builds a prototype and ensures that the simulation is ready in no time.

Empowering 112G SerDes Analysis

Consider a data center company developing a high-speed 112Gbps interface for their next-generation SoC. Working with Cadence IP for 112G long-reach serializer/deserializer (SerDes), they have access to the experts in the Cadence IP group to get the SerDes designed into their chip. To achieve the system specifications, they must ensure that the various pieces of interconnect from the high-speed SerDes and from the transmitter to the receiver are modeled accurately. They must also overcome the system analysis challenges such as system-level signal integrity, system-level power integrity, analysis of system power delivery across connectors and cables, and EM interference (EMI) and compatibility (EMC) analysis.

High-speed signaling such as in 112Gbps SerDes interface must have a high-fidelity interconnect design. Even a slight change in impedance can negatively impact bit error rate (BER). Conventional field solvers have limitations in analysis speed and capacity, and the engineers must simplify the structure or divide the layout into several segments to run within the constraints of the machine environment. Cadence can support them to model and analyze the full system, from the SerDes IP to the chip design and the interconnects. Our state-of-the-art distributed multiprocessing technology efficiently tackles the EM challenges encountered when designing complex 3D structures on chips, packages, PCBs, connectors, and cables, bringing true 3D analysis to any engineer with desktop, on-premises, or cloud HPC resources. The Cadence Clarity 3D Solver’s adaptive meshing quickly and efficiently ensures accurate modeling across a large frequency range.

Key Features

Major features of the Clarity 3D Solver include:

• Enhanced usability: Automatically matches computing resources available to the structure being solved so 3D experts and non-3D experts can get accurate results on time.

• Breakthrough parallelization: Allows engineering managers more flexibility when budgeting for computer configurations required for 3D simulation.

• Flexibility: Brings true 3D analysis to any engineer with desktop, on-premises, or cloud HPC resources.

• Maximized resources: Eliminates early termination due to computer resources being fully consumed if only a small number of cores is available.
• Availability to users of all design platforms: Easily reads design data from all standard chip, IC package, and PCB platforms.
• Integrated 3D solutions: Easily integrates with Cadence Allegro® Package Designer Plus SiP Layout Option and Virtuoso® and Allegro environments to optimize in the analysis tool and implement in the design tool without being redrawn.
• Model EM interface: Merges mechanical structures such as cables and connectors with their system design and models an EM interface as a single model.
• 3D Workbench: This 3D user interface incorporates a 3D mechanical CAD GUI for creating, editing, and importing 3D solid models for electrical analysis. You can bring in design data from popular MCAD formats such as ACIS, IGES, and STEP as well as the Cadence Allegro and Sigrity formats. 3D components are easily created with parameterization and equation expressions to allow for modeling flexibility and simulation optimization. 3D CAD geometry problems and misalignment errors can be quickly repaired with the Clarity 3D Solver’s 3D Workbench model clean-up functions. The advanced adaptive meshing algorithms allow you to automatically generate accurate meshes for small intricate 3D components to large complex electronic systems with enclosures.

The three key attributes of the Clarity 3D Solver are meshing, solver accuracy, and computation parallelism. A distributed matrix cuts the entire large matrix for adaptive meshing into diverse small matrices and decreases the peak memory and ensures time efficiency for each server. The parallelization technology ensures that both meshing and frequency sweeping can be partitioned and parallelized across as many computers, configurations, and cores available, reducing the time to solve complex structures by up to 10X. A significantly smaller memory footprint makes it cost-effective to run on a multitude of CPUs. These advantages make the cloud-ready Clarity 3D Solver an ideal choice to optimize a company’s cloud computing budget.

Conclusion

The Clarity 3D Solver helps you avoid costly implementations, engineering delays, product iterations, and field failures. It removes late-stage design iterations by accurately predicting how a product will perform in the lab. The Clarity 3D Solver provides efficiency improvement and communication between design and analysis teams, and provides integrated model extraction capabilities for chip, package, and PCB. It accelerates product development with complex 3D structure modeling with near-linear scalability in speed enhancement and memory reduction, while improving product reliability with fast and accurate interconnect extraction. The Clarity 3D Solver helps designers avoid design re-spins by identifying problems early in the design cycle, as well as improve product design with what-if analysis utilizing the 3D Workbench’s parameterization and user-defined equation expressions to easily edit, modify, and optimize mechanical structures.

With Clarity 3D solver, semiconductor and systems companies can design robust applications, address complex EM challenges involving complex 5G and 112G communication networks, advanced driver assistance system (ADAS), high-performance computing (HPC), machine learning (ML), and internet of things (IoT) applications with gold-standard accuracy.