Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
How much integrity is too much? If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are also more expensive than necessary and your decap mounting structures have vias in areas that could be better applied for signal routing. If you reduce the number of decaps, will you have less integrity? Will your PCB's Power Delivery Network (PDN) performance (and your performance as a designer) be challenged?
Successful selection of the type and quantity of decaps and their placement locations depend on many factors. Included in the factors are: device switching current, target impedance profiles, capacitance and inductance (ESL) of the decaps, mounting inductance of each decap and device, and PDN inductance between device and decap. Even with the availability of detailed simulation tools to verify PDN performance, it is often not clear how to make decap implementation tradeoffs. Pre-layout decisions tend to add more decaps than truly needed. Selection and placement is often based on experience and "best practices". And while it is easier to remove extra decaps than to add more during post-layout verification, over-design not only adds the cost of unneeded decaps, but may unnecessarily force use of extra PCB layers due to blocked routing channels that need not be blocked.
Cadence Sigrity OptimizePI provides an analytical basis upon which to make decisions regarding PDN design tradeoffs. Pre-layout guidance is provided for decap types and how many should be placed on the top/bottom of the design and under the devices. This helps to dramatically reduce over-design at an early stage in the design flow, where it can yield the greatest benefit to the overall design. Post-layout analysis considers thousands of design alternatives in a completely automated manner and provides a short list of optimal decap schemes from which to select the most appropriate tradeoff for your design. PDN performance is maximized while cost, area, and emissions are simultaneously minimized. Even for designs that have undergone pre-layout analysis, it is typical to reduce decap cost by 15% while maintaining or improving performance during post-layout optimization. For decap implementations that are over-designed from the beginning, the decap cost savings are often 50% or more with the potential for significant PDN performance improvements.
Grab a warm or frosty cold beverage and enjoy a demonstration of Cadence Sigrity OptimizePI. An 18-layer FPGA-based board is examined for which the 1.5V rail of the original design contained more than 120 decaps. This original design is observed to have impedance peaks, corresponding to high PDN noise, in the frequency range where significant energy will exist for typical switching circuits. SPOILER ALERT: OptimizePI reduced decap cost and improved performance.
You can see from the demonstration how easily design engineers, board layout designers, and power integrity experts alike can utilize OptimizePI to provide analytical guidance for their decap implementations.
Tell us about your experiences using OptimizePI.