Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Exposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the openings directly in the padstack definition for the bumps is perfect. But, what about for wire bond designs?
Fingers and power/ground rings need to be exposed so they can be bonded to, but visibility of surrounding metal should be minimized. At the same time, it is important that the openings themselves not have sharp corners which could cause manufacturing concerns like the mask getting peeled back.
As a result, it is not appropriate to use the solder mask pads in the finger pad definitions (which wouldn't help with the rings, regardless!). Instead, a smooth mask outline around sets of fingers in close proximity is the best approach.
How, then, do you go about making this happen? With the Cadence APD and SiP Layout tools in 16.6, the answer is the bond finger solder masking tool. Keep reading to learn more about what this handy tool allows you to do.
Near the end of your initial design of a substrate for a package with one or more wire bonded dies, it comes time to define the solder mask openings. APD and SiP Layout provide you with a tool specifically to accomplish this task. You can find it under the Manufacture -> Create Bond Finger Solder Mask menu item.
With a simple interface (see for yourself, below!), you get all the controls that you need. There are two modes to give you the flexibility you need, with different options for bond finger exposure and power/ground ring openings.
When creating mask openings for fingers, you should take special note of the field at the very bottom. By controlling the intent width, you can eliminate any potentially sharp corners on the inside of the mask shape between fingers. This way, you get a smooth, clean opening around an entire tier of fingers with one simple selection.
Conversely, for bonds to your rings, you can expose only the pieces of the ring which have bonds to them. The mask openings can even be trimmed to the edge of the shape to make sure no nearby clines are accidentally exposed.
Do you have a need to create these types of masks around a set of vias on your substrate layer? Do you have some pins, perhaps, where using the padstack-embedded solder mask pad shape is not suitable? Fret not. Turn on the "icp_soldermask_allow_pins" option in your User Preferences editor and you can define masks for these objects with the same settings you have when masking traditional fingers. How's that for flexibility?
Fear not! ECO and design revisions are a fact of life. When you receive an order that requires changes to the bond finger pattern, you can make those changes knowing that, when complete, the mask openings can be quickly and easily updated.
Using the same manufacturing command, make sure that you have the "Delete existing solder mask" option enabled at the top of the options (it is on in the screen shot above). This will automatically delete the old shapes as you select the fingers you have moved or added, leaving just the new mask. This ensures that you don't have overlapping masks that could result in undesirable outlines or - even worse - the exposure of clines and vias that are where one or more of the old fingers used to be.
Once you have your solder masks defined (or after updating them because of a design change request), it is important to validate that only the right objects are going to be exposed during manufacturing of your substrate.
The APD and SiP Layout tools provide you with a number of checks beyond the basic solder mask online DRCs. You can configure these under the Assembly worksheet in Constraint Manager and run them from the Manufacture -> Assembly Rules Checker... command, shown below with the 16.6 solder mask rules:
If you want to write your own checks, you can use the RAVEL tool to define custom rules. Or, for pure visualization of the metal exposed by the solder mask shapes (particularly useful for documentation purposes), you can use the layer compare tool set, which we covered in an earlier entry in this series. By doing a logical AND between the solder mask layer and the corresponding substrate conductor layer, you can create a layer showing only the metal that is visible through holes in the solder mask. There's even the option of viewing things in the 3D Viewer, where you can see the bond wires and their clearance from the masks as they get close to the substrate! Talk about choices!
Armed with these tools, are you eager to make your design flow more efficient? If you have an idea for how to make these tools even more powerful, we would love to hear it. Give your Cadence support representative a call and let us know your ideas. Just don't be surprised if, with the next software release, you see your idea realized in the tool!