3D-IC: System-Level Electrical and Thermal Challenges

3D-ICs (the latest technology for fitting more functionality onto a smaller chip) stack silicon wafers or dies on multiple layers and interconnects them vertically with the aim of providing better performance at reduced power.

Sounds great, but of course, the advantages of this increased design density come with the disadvantages of thermal issues, crosstalk, and power noise. A good way to address these issues and avoid expensive and time-consuming re-spins is through simulation during the system planning stage and through to signoff. 

To be successful, you need to understand thermal gradients, signal quality, and power delivery across chips, packages, and PCBs so you can uncover risks and optimize the design for maximum performance.

A Cadence TechTALK titled “Overcoming System-Level 3D-IC Electrical and Thermal Challenges” shows how you can use the Celsius Thermal Solver and Voltus solution to resolve system analysis challenges in 3D-IC design. The session covers how to perform 3D-IC chip-centric thermal analysis, package/PCB thermal analysis, interconnect modeling, and system-level signal quality and power distribution network (PDN) signoff.

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