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You read the requirements for a green card to Narnia, gathered the required documents, filled an application form, managed your schedules, traveled to the PR office, and after a long wait, you are told the application is rejected and that you need to go through the process again. You are informed that “something is not right” without being told exactly what went wrong. What follows is bitter disappointment and loss of time, money, and effort in investigating the real reason for the rejection. Don’t you wish there were some checks in place to warn you in time to make amends and avoid the unpleasant experience you had?
At least in the PCB design flow, you don’t need to go through this experience. Allegro X System Capture comes with built-in Design Integrity features that help with PCB design and the assurance that you won’t lose any time, money, effort, or sleep over designing a PCB. There won’t be any surprises or shocks awaiting you at the end of the design process.
Design Integrity includes a comprehensive list of audit rules that quickly scrutinize the design in one click and show violations as well as suggest corrections. The checks are strict, but in some cases, where you can live with an issue, you can waive it, and the violation is ignored.
The entire process of designing a PCB can be divided into the following phases for design integrity evaluation:
When starting a design, parts are placed on the design canvas. This requires complete information about the inventory of the available parts. The library management applications offer a seamless flow of information about the parts available. You connect the parts with wires and run the Audit Schematic check. A Schematic Audit Report is generated, flagging violations for connectivity checks, graphical checks, protocol checks, device checks, and electrical rule checks.
You can also run the circuit simulator for functional blocks within the schematic design. This increases your confidence in the electrical correctness of the design.
Now, to ensure the right current and voltage numbers on ICs and to avoid over-voltage damages and under-voltage lockouts, you have an easy way to ensure reliable operation. Power Topology Analyzer checks voltages and currents on power pins, visualizes the power flow, and shows it in a tree view. For example, if an IC pin has insufficient drive voltage, this is pointed out, and you can rectify the schematic and proceed with a reliable power distribution network.
You can quickly analyze the schematic for overstressed components and replace them with appropriately rated ones using the Electrical OverStress analysis (EOS). EOS comes in handy by providing voltage, current, power, and temperature (V-I-P-T) numbers for components by running electrical analysis on the complete schematic to become time- and memory-efficient, and therefore, cost-effective.
At this stage, you might think, “Wow! That was quick. I should now go ahead with the layout.” Design integrity says, “Hold on, buddy, what is your PCB application environment? For how long do you think this board will be functional?”
Here comes another one-click solution, Mean Time Between Failures (MTBF), to estimate the life of your PCB. There are a few life-estimation tools in the market, but they use V-I-P-T numbers obtained by heuristics for PCB life guesstimation. And it is no rocket science to understand that a good method has two qualifying traits - accuracy and simplicity. Our analysis uses the V-I-P-T numbers from EOS as initial fodder for MTBF.
The MTBF analysis considers your specific application environment and estimates the PCB life per the MIL-HDBK-217F-N2 or FIDES standard. After the analysis, you can refine the schematic by replacing prone-to-quick-failure parts with sturdier ones and recheck to ensure the PCB reaches the expected number of years you want it in play.
The MTBF Results dashboard displays the results as shown in the following figure:
The next step in bringing your creation to the real world is layout design.
As a first step towards layout design, you would start with placing the ICs and components with a larger footprint. These components will most likely be the hottest ones in the vicinity. We have another ace up our sleeve called Analyze Thermal Floorplan. I am sure Harry Potter Jr. will fancy this if he becomes a layout designer. With a single click (Swoosh!), you can get the temperature estimates of the placed components and identify the ones that seem prone to breaking down. The Thermal Floorplan Analysis Results dashboard displays the results as shown in the following figure:
Wearing the layout designer hat, you can then take immediate corrective actions at the schematic level by replacing the component with one at a higher-rated temperature or the layout level by keeping thermally sensitive components out of the hot zone and rerunning the thermal analysis of the floorplan. With minimal zero-cost iterations, the layout gets continually refined and optimized in the thermal domain.
Now, you are ready for the last phase. You can choose from various post-layout analysis tools for signal integrity checks. The finished PCB design can be electrically signed off.
Here is a summary of the entire PCB design analysis process:
I’ll be back soon with details of these analyses in more in-depth blog posts. Stay tuned.
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This ASCENT series is for the Allegro X System Capture product suite that includes applications and features, such as Allegro Pulse, Unified Search, Part Manager, Constraints Manager, Live BOM, Team Design, and System Reliability to name a few.
In this series of posts, we discover Allegro X System Capture and how you can use it for creating parts, libraries, and designs, reusing established IP, running design integrity checks, all the way to creating layout files while managing design costs, time to market, standards compliance, and providing access to non-EDA support functions.
So, whether you are a single designer wearing multiple hats or a large enterprise, Allegro X System Capture has something for you. Stay tuned as we share tips and tricks to smooth your ascent!