System Analysis Knowledge Bytes: A Step-by-Step Guide to Shorting Nets in Sigrity PowerSI and Other Layout-Based Analysis Tools

The System Analysis Knowledge Bytes blog series explores the capabilities and potential of the System Analysis tools offered by Cadence®. In addition to providing insight into the useful features and enhancements in this area, this series aims to broadcast the views of different bloggers and experts, who share their knowledge and experience on all things related to System Analysis.

Many times we need to short two nets on the PCB in a Sigrity tool, which is open in a real PCB. These nets could be signal nets or power/ground nets. In this post, we will understand how to short two nets and examine the impedance changes resulting from shorting the two nets.

We know that a capacitor consists of two electrical conductors that are separated by a distance. The space between the conductors may be filled with a vacuum or with an insulating material known as a dielectric. The capacitive reactance of a capacitor decreases as the frequency increases. So, the capacitive reactance is higher at lower frequencies and lower at higher frequencies.

In signal and power integrity analysis, the power and ground nets are the most important nets. The power and ground planes are in the inner layer of the PCB, separated by the dielectric layer. So, the power and ground planes together with the dielectric layer form a capacitance in the PCB.

In the following section, we will see that the capacitance reactance between the power and ground plane is very high, and it decreases as the frequency increases. We will then short the power and ground net by a resistance of 0.01ohm. Now the capacitance reactance will drop to 0.01ohm as it is parallel to the capacitance. 

Overview

This section describes how to select the nets and create nodes to place the component, which will create the short between the nodes. Then, run the simulation to get the short circuit impedance between the nodes. You will learn to do the following:

• Select the nets.
• Do open circuit impedance measurement.
• Define a component to make a short.
• Place components to nodes.
• Do simulation setup.
• Run the simulation with shorted components and check the difference between the results.
• Short by adding trace between nodes

Making a Short Between Two Nodes  

Let us consider shorting the Power (VDD) and the Ground (GND) net in the PCB. We will check the impedance of the nets when it is open and then measure it again when it is short.

To measure the impedance, go to the Layer Selection tab and select the layer in which you want to short it. You must select the nodes and connect the port.

Since it is a power net, the port impedance should be 1.0 ohm or less. Now, setup simulation frequencies and run the simulation.

When the simulation is complete, select the Z plot from the drop-down menu and change the X-axis to log scale.

You will see that the impedance is 2e6 ohm at the lower frequency range. This is due to the capacitance between the VDD and GND planes. As the frequency increases, the impedance reduces. Now, you will make a short circuit to the other end of the plane and measure the impedance.

The following video shows the steps to run the simulation.

To make a short circuit, you will create a resistance and connect between the VDD and GND nodes at the other end.

Go to Setup > Component Manager. The Component Manager window will open.

Click on New > New Model Definition > OK.

The New Model window will open.

Create a model, short_comp, with two nodes, 1 and 2, and a resistance of 0.01ohm between the two nodes. Click OK to close the New Model window.

Again, go to Component Manager and click on New > New Component > OK.

It will open the New Components window.

Select Definition Name as short_comp from the drop-down menu and write a RefDes name, say, R_short, and click OK.

A new component, R_short, will be created and assigned a value of 0.01 ohm.

To place the component between VDD and GND net, select another node of VDD and GND and place R_short and then run the simulation.

When the simulation is complete, you will see that the VDD and GND nets are shorted, and the impedance is reduced to 0.01 ohm at low frequency.

Another way to short two nodes is to go Edit > Trace > Add. Then, select VDD node and GND node. Once it is done, right-click and select Done.

The VDD and GND nodes are shorted.

Conclusion

This post covered the steps to short two nodes of VDD and GND nets by creating a resistance and connecting the two nodes. A trace can also be drawn between the two nodes, which will effectively short the two nodes. Please find the corresponding Rapid Adoptoin Kit (RAK) here which is accessible for all customers with a Cadence Online Support (COS) account.

Do You Have Access to the Cadence Support Portal?

4 simple steps to register on COS: Getting Started with Cadence Support Portal (Video)

You might also be interested in our free Online Training  Sigrity PowerDC and OptimizePI and/or in the following Training Byte Channel

Stay with us as we continue to explore what’s new in the world of Cadence Sigrity and Systems Analysis. For information about the most recent enhancements, check the Sigrity and Systems Analysis 2023.1 What's New. Happy reading!

Author of the RAK: Debabrata Das, Sr Principal Application Engineer

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