System Analysis Knowledge Bytes: Accelerating Early Stage Design Sign-Off Using PCIe 5.0 Compliance Kit in Topology Workbench

20 Jul 2022 • 4 minute read

The System Analysis Knowledge Bytes blog series explores the capabilities and potential of the System Analysis tools offered by Cadence^®. In addition to providing insight into the useful features and enhancements in this area, this series aims to broadcast the views of different bloggers and experts, who share their knowledge and experience on all things related to System Analysis.

Peripheral Component Interconnect express (PCIe) is one of the High-Speed interfaces that incorporates a paradigm shift in high bandwidth and data transfer. As a result, PCIe is used for the interconnections between High-Speed components of the computer expansion cards used for GPUs, WiFi Card,s video cards, SSDs, and so on. The vivid nature of PCIe combines high bandwidth with reasonable component costs and helps it grow in a fast manner.

In this blog, we will talk about how the CadenceAdvancedSI tools, which are packaged in the Topology Workbench environment, support the complete PCIe 5.0 channel characterization. This tool effectively addresses the challenges faced in power-aware Signal Integrity (SI) analysis for memories and other High-Speed interconnect interfaces.

Algorithmic Model Interfaces (AMI) and Input/Output Buffer Information Specification (IBIS) models in addition to various sub-circuits inside the topology exponentially enhance the power of the Topology Workbench environment. Consequently, the environment adds multiple figures of merit (FOMs) such as fast simulation run time, less memory consumption, high convergence factor, SSN characterization, eye diagram, timing jitter performance, and BER from bathtub curve, and so on.

Unlike transistor-level SPICE netlist simulations, the Topology Workbench environment imbibes high-performance computing for expeditious run time. Therefore, this environment provides latent solutions for SystemSI (SerDes) and high-speed compliance kit (PCIe, HDMI, MIPI-C-PHY and MIPI-M-PHY, USB, 100Base, and so on).

Figure: Interconnections and Waveforms in Topology Workbench

PCIe 5.0 Compliance Kit (Channel and Crosstalk Analysis)

In Topology Workbench, the PCIe 5.0 compliance kit (Channel and Crosstalk analysis) empowers the SI, PI, and PCB engineers to surmount various SI/PI challenges and alleviate time for faster design sign-off. Moreover, you can analyze various required FOMs for High-Speed Interfaces early in the design cycle using the “what if” exploration scenarios for reduced design iterations and time to market.

Figure: PCIe 5.0 Channel Analysis with Compliance Report in Topology Workbench

For Channel and Crosstalk Analysis of PCIe 5.0 inherent Compliance Kit, the SI, PI, and PCB engineers require stimulus definition, model selection and Transmitter Jitter and Noise (Frequency Offset, Transition Random Jitter and Transition Deterministic Jitter) to generate SI performance metrics such as, Eye Diagram, Transmitter and Receiver Insertion and Return Loss, and Probability Density Function (PDF) plot. The SI, PI, and PCB engineers can also easily create their own complex High-Speed designs and observe the complete SI performance metrics.

Figure: PDF Plot for PCIe 5.0 Channel Analysis

Topology Workbench also supports the compliance report generation for crosstalk counter-part analysis of PCIe 5.0 by understanding each sub-circuit and the related requirements. Inherent High-Speed Compliance kits in the Topology Workbench environment enhance the First Pass Success by reducing design cycle iterations for high-speed interfaces like, PCIe, HDMI, MIPI-C-PHY and MIPI-M-PHY, USB, 100Base and so on.

Figure: PCIe 5.0 Crosstalk Analysis in Topology Workbench environment

Similarly, to obtain all performance parameters for PCIe 5.0 Crosstalk analysis, you need to deselect the Stressed/Swept Jitter option in the choose compliance items form prior to the report generation. The compliance report generated for channel and crosstalk analysis as shown below includes SI performance metrics such as, Eye Height, Eye Width, Eye Mask, BER, Insertion Loss, and Return Loss. In addition, the report shows the results for each selected compliance item.

Figure: PCIe 5.0 Crosstalk Analysis with Compliance Report and PDF Plot

This wraps up our summary of PCIe 5.0 Compliance Kit. Stay tuned as we explore other highlights from the world of Cadence Sigrity and Systems Analysis.

Akshaya Kumar