• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. System, PCB, & Package Design
  3. Analog/RF chip designers don't care about the Package?
SiPper
SiPper

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
CDNS - RequestDemo

Try Cadence Software for your next design!

Free Trials
Analog and RF SiP design
Analog chip design
IC Packaging & SiP design
Virtuoso
IC Package Physical layout and co-design
design chain

Analog/RF chip designers don't care about the Package?

24 Aug 2008 • Less than one minute read

So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will go into!! 

Now I kinda understand that this could be true for chips that go into leadframe packages, but...for example, lets take a complex wireless radio chip design that end up in routable substrate package (BGA/LGA), now the design team surely needs to consider the package at some stage? 

Do these circuits designers really ignore package effects? Do they never communicate with the package designer? not even to send them a basic footprint and pinout of the chip?

I'm hoping that some of you do care, that you need to "interface" with the package design team, and if so, how is it done today, what works, what doesn't and what makes you want to rip your hair out?  So come on, let me know, let eveyone know!


CDNS - RequestDemo

Have a question? Need more information?

Contact Us

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information